dc.creator | Linares Barranco, Bernabé | es |
dc.creator | Sánchez Sinencio, Edgar | es |
dc.creator | Rodríguez Vázquez, Ángel Benito | es |
dc.creator | Huertas Díaz, José Luis | es |
dc.date.accessioned | 2018-06-27T13:46:10Z | |
dc.date.available | 2018-06-27T13:46:10Z | |
dc.date.issued | 1993 | |
dc.identifier.citation | Linares Barranco, B., Sánchez Sinencio, E., Rodríguez Vázquez, Á.B. y Huertas Díaz, J.L. (1993). A CMOS analog adaptive BAM with on-chip learning and weight refreshing. IEEE Transactions on Neural Networks, 4 (3), 445-455. | |
dc.identifier.issn | 1045-9227 | es |
dc.identifier.issn | 1941-0093 | es |
dc.identifier.uri | https://hdl.handle.net/11441/76509 | |
dc.description.abstract | In this paper we will extend the transconductance-mode (T-mode) approach [1] to implement analog continuous-time neural network hardware systems to include on-chip Hebbian learning and on-chip analog weight storage capability. The demonstration vehicle used is a 5 + 5 neurons bidirectional associative memory (BAM) prototype fabricated in a standard 2-μm double-metal double-polysilicon CMOS process (through and thanks to MOSIS). Mismatches and nonidealities in learning neural hardware are supposed not to be critical if on-chip learning is available, because they will be implicitly compensated. However, mismatches in the learning circuits themselves cannot always be compensated. This mismatch is specially important if the learning circuits use transistors operating in weak inversion. In this paper we will estimate the expected mismatch between learning circuits in the BAM network prototype and evaluate its effect on the learning performance, using theoretical computations and Monte Carlo Hspice simulations. Afterwards we will verify these theoretical predictions with the experimentally measured results on the test vehicle prototype. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | IEEE Transactions on Neural Networks, 4 (3), 445-455. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | A CMOS analog adaptive BAM with on-chip learning and weight refreshing | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.publisherversion | http://dx.doi.org/10.1109/72.217187 | es |
dc.identifier.doi | 10.1109/72.217187 | es |
idus.format.extent | 11 p. | es |
dc.journaltitle | IEEE Transactions on Neural Networks | es |
dc.publication.volumen | 4 | es |
dc.publication.issue | 3 | es |
dc.publication.initialPage | 445 | es |
dc.publication.endPage | 455 | es |