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A modified ART 1 algorithm more suitable for VLSI implementations

 

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dc.creator Serrano Gotarredona, María Teresa es
dc.creator Linares Barranco, Bernabé es
dc.date.accessioned 2018-06-26T13:45:00Z
dc.date.available 2018-06-26T13:45:00Z
dc.date.issued 1996
dc.identifier.citation Serrano Gotarredona, M.T. y Linares Barranco, B. (1996). A modified ART 1 algorithm more suitable for VLSI implementations. Neural Networks, 9 (6), 1025-1043.
dc.identifier.issn 0893-6080 es
dc.identifier.uri https://hdl.handle.net/11441/76479
dc.description.abstract This paper presents a modification to the original ART 1 algorithm (Carpenter and Grossberg, 1987a, A massively parallel architecture for a self-organizing neural pattern recognition machine, Computer Vision, Graphics, and Image Processing, 37, 54–115) that is conceptually similar, can be implemented in hardware with less sophisticated building blocks, and maintains the computational capabilities of the originally proposed algorithm. This modified ART 1 algorithm (which we will call here ART 1m) is the result of hardware motivated simplifications investigated during the design of an actual ART 1 chip [Serrano-Gotarredona et al., 1994, Proc. 1994 IEEE Int. Conf. Neural Networks (Vol. 3, pp. 1912–1916); Serrano-Gotarredona and Linares-Barranco, 1996, IEEE Trans. VLSI Systems, (in press)]. The purpose of this paper is simply to justify theoretically that the modified algorithm preserves the computational properties of the original one and to study the difference in behavior between the two approaches. es
dc.format application/pdf es
dc.language.iso eng es
dc.publisher Elsevier es
dc.relation.ispartof Neural Networks, 9 (6), 1025-1043.
dc.rights Attribution-NonCommercial-NoDerivatives 4.0 Internacional *
dc.rights.uri http://creativecommons.org/licenses/by-nc-nd/4.0/ *
dc.title A modified ART 1 algorithm more suitable for VLSI implementations es
dc.type info:eu-repo/semantics/article es
dc.type.version info:eu-repo/semantics/submittedVersion es
dc.rights.accessrights info:eu-repo/semantics/openAccess es
dc.contributor.affiliation Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores es
idus.format.extent 30 p. es
dc.journaltitle Neural Networks es
dc.publication.volumen 9 es
dc.publication.issue 6 es
dc.publication.initialPage 1025 es
dc.publication.endPage 1043 es
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