dc.creator | Serrano Gotarredona, María Teresa | es |
dc.creator | Andreou, Andreas G. | es |
dc.creator | Linares Barranco, Bernabé | es |
dc.date.accessioned | 2018-06-22T13:32:45Z | |
dc.date.available | 2018-06-22T13:32:45Z | |
dc.date.issued | 1999 | |
dc.identifier.citation | Serrano Gotarredona, M.T., Andreou, A.G. y Linares Barranco, B. (1999). AER image filtering architecture for vision-processing systems. IEEE Transactions on Circuits and Systems I - Fundamental Theory and Applications, 46 (9), 1064-1071. | |
dc.identifier.issn | 1057-7122 | es |
dc.identifier.uri | https://hdl.handle.net/11441/76405 | |
dc.description.abstract | A VLSI architecture is proposed for the realization of real-time two-dimensional (2-D) image filtering in an address-event-representation (AER) vision system. The architecture is capable of implementing any convolutional kernel F(x,y) as long as it is decomposable into x-axis and y-axis components, i.e., F(x, y) = H(x)V(y), for some rotated coordinate system {x, y} and if this product can be approximated safely by a signed minimum operation. The proposed architecture is intended to be used in a complete vision system, known as the boundary contour system and feature contour system (BCS-FCS) vision model, proposed by Grossberg and collaborators. The present paper proposes the architecture, provides a circuit implementation using MOS transistors operated in weak inversion, and shows behavioral simulation results at the system level operation and some electrical simulations. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | IEEE Transactions on Circuits and Systems I - Fundamental Theory and Applications, 46 (9), 1064-1071. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Analog integrated circuits | es |
dc.subject | Communication systems | es |
dc.subject | Convolution circuits | es |
dc.subject | Gabor filters | es |
dc.subject | Image analysis | es |
dc.subject | Image segmentation | es |
dc.subject | Neural networks | es |
dc.subject | Nonlinear circuits | es |
dc.subject | Subthreshold circuits | es |
dc.title | AER image filtering architecture for vision-processing systems | es |
dc.type | info:eu-repo/semantics/article | es |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.relation.publisherversion | http://dx.doi.org/10.1109/81.788808 | es |
dc.identifier.doi | 10.1109/81.788808 | es |
idus.format.extent | 8 p. | es |
dc.journaltitle | IEEE Transactions on Circuits and Systems I - Fundamental Theory and Applications | es |
dc.publication.volumen | 46 | es |
dc.publication.issue | 9 | es |
dc.publication.initialPage | 1064 | es |
dc.publication.endPage | 1071 | es |