dc.creator | Rodríguez Villegas, Esther | es |
dc.creator | Avedillo de Juan, María José | es |
dc.creator | Quintana Toledo, José María | es |
dc.creator | Huertas Sánchez, Gloria | es |
dc.creator | Rueda Rueda, Adoración | es |
dc.date.accessioned | 2018-06-21T13:05:26Z | |
dc.date.available | 2018-06-21T13:05:26Z | |
dc.date.issued | 2000 | |
dc.identifier.citation | Rodríguez Villegas, E., Avedillo de Juan, M.J., Quintana Toledo, J.M., Huertas Sánchez, G. y Rueda Rueda, A. (2000). nu MOS-based sorter for arithmetic applications. VLSI Design, 11 (2), 129-136. | |
dc.identifier.issn | 1065-514X | es |
dc.identifier.issn | 1563-5171 | es |
dc.identifier.uri | https://hdl.handle.net/11441/76361 | |
dc.description.abstract | The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing some arithmetic demonstrators. In particular, both an (8×8)-multiplier and a (15,4) counter which use a sorter as the main building block have been implemented. Traditional disadvantages of binary sorters such as their hardware intensive nature are avoided by using νMOS circuits. It allows both an improving of previous results for multipliers based on a similar architecture, and to obtain a new type of counter which shows a reduced delay when compared to a conventional implementation. | es |
dc.description.sponsorship | Comisión Interministerial de Ciencia y Tecnología TIC97-0648 | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Hindawi Publishing Corporation | es |
dc.relation.ispartof | VLSI Design, 11 (2), 129-136. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | vMOS circuits | es |
dc.subject | Threshold logic | es |
dc.subject | Sorter circuits | es |
dc.subject | Arithmetic circuits | es |
dc.title | nu MOS-based sorter for arithmetic applications | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | TIC97-0648 | es |
dc.relation.publisherversion | http://dx.doi.org/10.1155/2000/57240 | es |
dc.identifier.doi | 10.1155/2000/57240 | es |
idus.format.extent | 9 p. | es |
dc.journaltitle | VLSI Design | es |
dc.publication.volumen | 11 | es |
dc.publication.issue | 2 | es |
dc.publication.initialPage | 129 | es |
dc.publication.endPage | 136 | es |
dc.contributor.funder | Comisión Interministerial de Ciencia y Tecnología (CICYT). España | |