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dc.creatorAvedillo de Juan, María Josées
dc.creatorNúñez Martínez, Juanes
dc.date.accessioned2018-04-13T14:21:42Z
dc.date.available2018-04-13T14:21:42Z
dc.date.issued2015
dc.identifier.citationAvedillo de Juan, M.J. y Nuñez Martínez, J. (2015). Improving speed of tunnel FETs logic circuits. Electronics Letters, 51 (21), 1702-1704.
dc.identifier.issn0013-5194 (impreso)es
dc.identifier.issn1350-911X (electrónico)es
dc.identifier.urihttps://hdl.handle.net/11441/72851
dc.description.abstractTunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigating to overcome power density and energy inefficiency exhibited by CMOS technology. These transistors exhibit asymmetric conduction which can cause sustained noise voltage pulses (bootstrapping) within digital TFETs circuits leading to delay degradation. In this paper, we propose a minor modification of the complementary gate topology to avoid the bootstrapping problem and show its impact on speed at the circuit level. Speed improvements up to 33% have been obtained for 8-bit Ripple Carry Adders when implemented with our solution.es
dc.description.sponsorshipMinisterio de Ecoomía y Competitividad TEC2013-40670-Pes
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherInstitute of Electrical and Electronics Engineerses
dc.relation.ispartofElectronics Letters, 51 (21), 1702-1704.
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.titleImproving speed of tunnel FETs logic circuitses
dc.typeinfo:eu-repo/semantics/articlees
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones
dc.rights.accessrightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.projectIDTEC2013-40670-Pes
dc.relation.publisherversionhttps://doi.org/10.1049/el.2015.2416es
dc.identifier.doi10.1049/el.2015.2416es
idus.format.extent2 p.es
dc.journaltitleElectronics Letterses
dc.publication.volumen51es
dc.publication.issue21es
dc.publication.initialPage1702es
dc.publication.endPage1704es
dc.contributor.funderMinisterio de Economia, Industria y Competitividad (MINECO). España

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