dc.creator | Fernández Pérez, José María | es |
dc.creator | Sánchez Fernández, Francisco J. | es |
dc.creator | Carmona Galán, Ricardo | es |
dc.date.accessioned | 2018-03-22T16:04:18Z | |
dc.date.available | 2018-03-22T16:04:18Z | |
dc.date.issued | 2007 | |
dc.identifier.citation | Fernández Pérez, J.M., Sánchez Fernández, F.J. y Carmona Galán, R. (2007). Performance evaluation and limitations of a vision system on a reconfigurable/programmable chip. Journal of Universal Computer Science, 13 (3), 440-453. | |
dc.identifier.issn | 0948-695X (impreso) | es |
dc.identifier.issn | 0948-6968 (electrónico) | es |
dc.identifier.uri | https://hdl.handle.net/11441/71280 | |
dc.description.abstract | This paper presents a survey of the characteristics of a vision system implemented in
a reconfigurable/programmable chip (FPGA). System limitations and performance have been
evaluated in order to derive specifications and constraints for further vision system synthesis.
The system hereby reported has a conventional architecture. It consists in a central
microprocessor (CPU) and the necessary peripheral elements for data acquisition, data storage
and communications. It has been designed to stand alone, but a link to the programming and
debugging tools running in a digital host (PC) is provided. In order to alleviate the
computational load of the central microprocessor, we have designed a visual co-processor in
charge of the low-level image processing tasks. It operates autonomously, commanded by the
CPU, as another system peripheral. The complete system, without the sensor, has been
implemented in a single reconfigurable chip as a SOPC. The incorporation of a dedicated visual
co-processor, with specific circuitry for low-level image processing acceleration, enhances the
system throughput outperforming conventional processing schemes. However, timemultiplexing
of the dedicated hardware remains a limiting factor for the achievable peak
computing power. We have quantified this effect and sketched possible solutions, like
replication of the specific image processing hardware. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Technische Universität Graz | es |
dc.relation.ispartof | Journal of Universal Computer Science, 13 (3), 440-453. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Image processing | es |
dc.subject | System-on-a-programmable-chip implementation | es |
dc.subject | Algorithms implemented in hardware [Integrated Circuits] | es |
dc.subject | Hardware architecture [Computer Graphics] | es |
dc.title | Performance evaluation and limitations of a vision system on a reconfigurable/programmable chip | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/publishedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.relation.publisherversion | http://dx.doi.org/10.3217/jucs-013-03-0440 | es |
dc.identifier.doi | 10.3217/jucs-013-03-0440 | es |
idus.format.extent | 13 P. | es |
dc.journaltitle | Journal of Universal Computer Science | es |
dc.publication.volumen | 13 | es |
dc.publication.issue | 3 | es |
dc.publication.initialPage | 440 | es |
dc.publication.endPage | 453 | es |