dc.creator | Acosta Jiménez, Antonio José | es |
dc.creator | Bellido Díaz, Manuel Jesús | es |
dc.creator | Valencia Barrero, Manuel | es |
dc.creator | Barriga Barros, Ángel | es |
dc.creator | Jiménez, R. | es |
dc.creator | Huertas Díaz, José Luis | es |
dc.date.accessioned | 2017-07-27T09:06:08Z | |
dc.date.available | 2017-07-27T09:06:08Z | |
dc.date.issued | 1995 | |
dc.identifier.citation | Acosta, A.J., Bellido Díaz, M.J., Valencia Barrero, M., Barriga, A., Jiménez, R. y Huertas, J.L. (1995). New CMOS VLSI Linear Self-Timed Architectures. En Second Working Conference on Asynchronous Design Methodologies, London, UK. | |
dc.identifier.isbn | 0-8186-7098-3 | es |
dc.identifier.uri | http://hdl.handle.net/11441/63282 | |
dc.description.abstract | The implementation of digital signal processor circuits
via self-timed techniques is currently a valid altemative
to solve some problems encountered in synchronous
VLSI circuits. However; a main difference between synchronous
and asynchronous circuits is the hardware resources
needed to implement asynchronous circuits. This
communication presents four less-costly alternatives to a
previously reported linear selftimed architecture, and
their application in the design of FIFO memories. Furthermore,
the integration and characterization in the laboratory
of prototypes of these FIFOs are presented. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.relation.ispartof | Second Working Conference on Asynchronous Design Methodologies (1995), p 14-23 | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | New CMOS VLSI Linear Self-Timed Architectures | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/publishedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/514638/ | |
dc.identifier.doi | 10.1109/WCADM.1995.514638 | es |
idus.format.extent | 10 | es |
dc.publication.initialPage | 14 | es |
dc.publication.endPage | 23 | es |
dc.eventtitle | Second Working Conference on Asynchronous Design Methodologies | es |
dc.eventinstitution | London, UK | es |