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ASIC-in-the-loop methodology for verification of piecewise affine controllers
dc.creator | Martínez Rodríguez, Macarena Cristina | es |
dc.creator | Brox Jiménez, Piedad | es |
dc.creator | Castro, Javier | es |
dc.creator | Tena Sánchez, Erica | es |
dc.creator | Acosta Jiménez, Antonio José | es |
dc.creator | Baturone Castillo, María Iluminada | es |
dc.date.accessioned | 2017-03-23T12:28:57Z | |
dc.date.available | 2017-03-23T12:28:57Z | |
dc.date.issued | 2012 | |
dc.identifier.citation | Martínez Rodríguez, M.C., Brox Jiménez, P., Castro, J., Tena Sánchez, E., Acosta Jiménez, A.J. y Baturone Castillo, M.I. (2012). ASIC-in-the-loop methodology for verification of piecewise affine controllers. En Comunicación presentada al "19th IEEE International Conference on Electronics, Circuits and Systems" (388-391), Sevilla: Institute of Electrical and Electronics Engineers. | |
dc.identifier.isbn | 978-1-4673-1261-5 | es |
dc.identifier.uri | http://hdl.handle.net/11441/56154 | |
dc.description.abstract | This paper exposes a hardware-in-the-loop metho- dology to verify the performance of a programmable and confi- gurable application specific integrated circuit (ASIC) that imple- ments piecewise affine (PWA) controllers. The ASIC inserted into a printed circuit board (PCB) is connected to a logic analyzer that generates the input patterns to the ASIC (in particular, the values to program the memories, configuration parameters, and values of the input signals). The output provided by the ASIC is also taken by the logic analyzer. A Matlab program controls the logic analyzer to verify the PWA controller implemented by the ASIC in open-loop as well as in closed-loop configurations. | es |
dc.description.sponsorship | Comunidad Europea FP7-INFSO-ICT-248858 | es |
dc.description.sponsorship | Gobierno Español TEC2011-24319 | es |
dc.description.sponsorship | Junta de Andalucía P08-TIC-03674 | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | Comunicación presentada al "19th IEEE International Conference on Electronics, Circuits and Systems" (2012), pp. 388-391. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | ASIC-in-the-loop methodology for verification of piecewise affine controllers | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | EC/FP7/248858 | es |
dc.relation.projectID | TEC2011-24319 | es |
dc.relation.projectID | P08-TIC-03674 | es |
dc.relation.publisherversion | http://dx.doi.org/10.1109/ICECS.2012.6463721 | es |
dc.identifier.doi | 10.1109/ICECS.2012.6463721 | es |
idus.format.extent | 4 p. | es |
dc.publication.initialPage | 388 | es |
dc.publication.endPage | 391 | es |
dc.eventtitle | Comunicación presentada al "19th IEEE International Conference on Electronics, Circuits and Systems" | es |
dc.eventinstitution | Sevilla | es |