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Gate-Level Simulation of CMOS Circuits Using the IDDM Model

 

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dc.creator Bellido Díaz, Manuel Jesús es
dc.creator Juan Chico, Jorge es
dc.creator Ruiz de Clavijo Vázquez, Paulino es
dc.creator Acosta Jiménez, Antonio José es
dc.creator Valencia Barrero, Manuel es
dc.date.accessioned 2017-01-19T09:47:22Z
dc.date.available 2017-01-19T09:47:22Z
dc.date.issued 2001
dc.identifier.citation Bellido Díaz, M.J., Juan Chico, J., Ruiz de Clavijo Vázquez, P., Acosta Jiménez, A.J. y Valencia Barrero, M. (2001). Gate-Level Simulation of CMOS Circuits Using the IDDM Model. En ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (483-486), Sidney, Australia: IEEE Computer Society.
dc.identifier.isbn 0-7803-6685-9 es
dc.identifier.uri http://hdl.handle.net/11441/52452
dc.description.abstract Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the extension to gates of the Inertial and Degradation Delay Model for logic timing simulation which is able to take account of the propagation of arbitrarily narrow pulses. As a result, the model is ready to be applied to the simulation and verification of complex circuits. Simulation results show an accuracy similar to HSPICE and greatly improved precision over conventional delay models. es
dc.description.sponsorship Ministerio de Ciencia y Tecnología TIC 2000-1350
dc.format application/pdf es
dc.language.iso eng es
dc.publisher IEEE Computer Society es
dc.relation.ispartof ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (2001), p 483-486
dc.rights Attribution-NonCommercial-NoDerivatives 4.0 Internacional *
dc.rights.uri http://creativecommons.org/licenses/by-nc-nd/4.0/ *
dc.title Gate-Level Simulation of CMOS Circuits Using the IDDM Model es
dc.type info:eu-repo/semantics/conferenceObject es
dc.type.version info:eu-repo/semantics/publishedVersion es
dc.rights.accessrights info:eu-repo/semantics/openAccess es
dc.contributor.affiliation Universidad de Sevilla. Departamento de Tecnología Electrónica es
dc.contributor.affiliation Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo es
dc.relation.projectID TIC 2000-1350
dc.relation.publisherversion http://ieeexplore.ieee.org/document/922090/ es
dc.identifier.doi 10.1109/ISCAS.2001.922090 es
idus.format.extent 4 es
dc.publication.initialPage 483 es
dc.publication.endPage 486 es
dc.eventtitle ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems es
dc.eventinstitution Sidney, Australia es
dc.relation.publicationplace USA es
dc.contributor.funder Ministerio de Ciencia y Tecnología (MCYT). España
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