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dc.contributor.editorZarandy, Akos
dc.creatorZarandy, Akos
dc.creatorRekeczky, Csaba
dc.creatorFöldesy, P.
dc.creatorCarmona Galán, Ricardo
dc.creatorLiñán Cembrano, Gustavo
dc.creatorGergely, S.
dc.creatorRodríguez Vázquez, Ángel Benito
dc.creatorRoska, Tamás
dc.date.accessioned2016-01-25T12:59:48Z
dc.date.available2016-01-25T12:59:48Z
dc.date.issued2011
dc.identifier.isbn978-1-4419-6474-8es
dc.identifier.urihttp://hdl.handle.net/11441/33242
dc.descriptionhttp://digital.csic.es/handle/10261/83126es
dc.description.abstractVertically integrated focal-plane sensor-processor chip design, combining image sensor with mixed-signal and digital processor arrays on a four layer structure is introduced. The mixed-signal processor array is designed to perform early image processing, while the role of the digital processor array is to accomplish foveal processing. The architecture supports multiscale, multifovea processing. The chip has been designed on a 0.15um feature sized 3DM2 SOI technology provided by MIT Lincoln Laboratory.es
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherSpringer Science+Business Mediaes
dc.relation.ispartofFocal-Plane Sensor-Processor Chips, 181-208es
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.titleVISCUBE: A multi-layer vision chipes
dc.typeinfo:eu-repo/semantics/bookPartes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/publishedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.publisherversionhttp://dx.doi.org/10.1007/978-1-4419-6475-5_8es
dc.identifier.doihttp://dx.doi.org/10.1007/978-1-4419-6475-5_8es
dc.identifier.idushttps://idus.us.es/xmlui/handle/11441/33242

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