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Improving the design process of VLSI circuits by means of a hardware debugging system: UNSHADES-1 framework
dc.creator | Aguirre Echanove, Miguel Ángel | |
dc.creator | Tombs, J. N. | |
dc.creator | Torralba Silgado, Antonio Jesús | |
dc.creator | García Franquelo, Leopoldo | |
dc.date.accessioned | 2015-05-29T14:23:53Z | |
dc.date.available | 2015-05-29T14:23:53Z | |
dc.date.issued | 2002 | |
dc.identifier.isbn | 0-7803-7474-6 | es |
dc.identifier.uri | http://hdl.handle.net/11441/25107 | |
dc.description.abstract | Due to the increase in size and complexity of VLSI integrated circuits, new design tools are becoming needed. Telecommunications and Electronic Industry demand designs that integrate intensive digital signal processing blocks and complex control tasks. Rapid Prototyping techniques introduce a new stage into the design flow that overcome the drawbacks of simulation stage and shorten design times. Advanced FPGAs can host the design for its emulation and can run inserted into the final system. The benefits of their use go beyond the simple rapid prototyping approach, and are able to provide additional information and other useful tasks that will be presented in this paper. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | IEEE | es |
dc.relation.ispartof | 28th Annual Conference Of The IEEE Industrial Electronics Society (IECON 02), 3, 2544 - 2547. IEEE | es |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | Improving the design process of VLSI circuits by means of a hardware debugging system: UNSHADES-1 framework | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Ingeniería Electrónica | es |
dc.relation.publisherversion | 10.1109/IECON.2002.1185374 | es |
dc.identifier.idus | https://idus.us.es/xmlui/handle/11441/25107 |
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