Digital test design with an "ad hoc" strategy for an industrial ASIC with large dimension

Abstract

The development of digital ASIC's with a large area states a lot of doubts when the ingenieer must design a test strategy. The design of an industrial circuit advises a test to be made quite similar to the normal field functioning. If the size of the die is large or quite complex this idea can be unreachable. The techniques of automatic test maybe relevant, thought it should be increased the cell and routing area. If the circuit has been designed with a hierarchical manner with separated blocks, or works with some precompiled megacells, the application of these techniques can be inadvisable, so that we suggest a mixed solution. In this paper we describes a set os a “ad hoc” strategies for the construction of a test for a large digital circuit, it has been introduced soma additional simple circuits able to make visible some part of the whole chip. Those ideas have been introduced in an industrial circuit which today is being manufactured.