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Ponencia
New high performance second generation CMOS current conveyor
dc.creator | Marri, Swathi | |
dc.creator | Ramírez Angulo, Jaime | |
dc.creator | López Martín, Antonio | |
dc.creator | González Carvajal, Ramón | |
dc.date.accessioned | 2015-03-12T10:17:07Z | |
dc.date.available | 2015-03-12T10:17:07Z | |
dc.date.issued | 2009 | |
dc.identifier.uri | http://hdl.handle.net/11441/23445 | |
dc.description.abstract | A new high performance second-generation CMOS current conveyor architecture is presented. It is built using a differential flipped voltage follower as its input buffer stage and a cascode current mirror as output stage. It is characterized by very low output impedance. It provides gain independent high bandwidth when used to implement a programmable gain voltage amplifier. Simulation and experimental results in AMI 0.5µm CMOS technology are provided to validate the characteristics of the design. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.relation.ispartof | XXIV Conference on Design of Circuits and Integrated Systems: Zaragoza, 18-20 de noviembre 2009 | es |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Analog integrated circuits | es |
dc.subject | Current mode signal processing | en |
dc.subject | Current conveyor | en |
dc.title | New high performance second generation CMOS current conveyor | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Ingeniería Electrónica | es |
dc.identifier.idus | https://idus.us.es/xmlui/handle/11441/23445 |
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