Listar Artículos (Instituto de Microelectrónica de Sevilla (IMSE-CNM)) por agencia financiadora "Junta de Andalucía"
Mostrando ítems 1-20 de 26
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A 32 x 32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput
(IEEE Computer Society, 2011)This paper describes a convolution chip for event-driven vision sensing and processing systems. As opposed to conventional ...
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A 515 nW, 0-18 dB programmable gain analog-to-digital converter for in-channel neural recording interfaces
(Institute of Electrical and Electronics Engineers, 2014)This paper presents a low-area low-power Switched-Capacitor (SC)-based Programmable-Gain Analog-to-Digital Converter ...
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A Customizable Thermographic Imaging System for Medical Image Acquisition and Processing
(Institute of Electrical and Electronics Engineers, 2022)A custom system has been developed for medical image acquisition and processing in both the visible and the infrared (IR) ...
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A Low-Latency, Low-Power CMOS Sun Sensor for Attitude Calculation Using Photovoltaic Regime and On-Chip Centroid Computation
(Institute of Electrical and Electronics Engineers, 2023)The demand for sun sensors has skyrocketed in the last years due to the huge expected deployment of satellites associated ...
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A microscopy technique based on bio-impedance sensors
(Elsevier, 2012)It is proposed a microscopy for cell culture applications based on impedance sensors. The imagined signals are measured ...
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A Mobile Platform for Movement Tracking Based on a Fast-Execution-Time Optical-Flow Algorithm
(Institute of Electrical and Electronics Engineers, 2022)A multi-purpose mechanical platform to track moving objects in three-dimensional space has been developed. It is composed ...
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A Procedure for Alternate Test Feature Design and Selection
(Institute of Electrical and Electronics Engineers, 2015)This paper is a practical illustration of the adoption of alternate tests based upon the judicious selection of the set ...
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A self-powered asynchronous image sensor with TFS operation
(Institute of Electrical and Electronics Engineers Inc., 2023-04-01)This article presents a self-powered image sensor with a novel pixel architecture with energy harvesting capabilities. ...
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All-MOS implementation of RC networks for time-controlled Gaussian spatial filtering
(Wiley-Blackwell, 2012)This paper addresses the design and VLSI implementation of MOS-based RC networks capable of performing time-controlled ...
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Analog sinewave signal generators for mixed-signal built-in test applications
(Springer, 2011)This work presents a technique for the generation of analog sinusoidal signals with high spectral quality and reduced ...
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Autoregressive time series prediction by means of fuzzy inference systems using nonparametric residual variance estimation
(Elsevier, 2010)We propose an automatic methodology framework for short- and long-term prediction of time series by means of fuzzy inference ...
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Cell-culture real time monitoring based on bio-impedance measurements
(International Frequency Sensor Association, 2012)This paper proposes the application of a cell-microelectrode model in cell biometry experiments, using the cell-electrode ...
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Closed-loop Simulation Method for Evaluation of Static Offset in Discrete-Time Comparators
(Institute of Electrical and Electronics Engineers, 2014)This paper presents a simulation-based method for evaluating the static offset in discrete-time comparators. The proposed ...
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Context-dependent transformation of Pareto-optimal performance fronts of operational amplifiers
(Springer, 2012)The use of Pareto-optimal performance fronts in emerging design methodologies for analog integrated circuits is a keystone ...
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Determination of the Time Constant Distribution of a Defect-Centric Time-Dependent Variability Model for Sub-100-nm FETs
(IEEE, 2022)The origin of some Time-Dependent Variability phenomena in FET technologies has been attributed to the charge carrier ...
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Domino inspired MOBILE networks
(Institute of Electrical and Electronics Engineers, 2012)MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly ...
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Effects of buffer insertion on the average/peak power ratio in CMOS VLSI digital circuits
(Society of Photo-optical Instrumentation Engineers, 2007)The buffer insertion has been a mechanism widely used to increase the performances of advanced VLSI digital circuits and ...
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Efficient realisation of MOS-NDR threshold logic gates
(Wiley Open Access, 2009-11-05)A novel realisation of inverted majority gates based on a programmable MOS-NDR device is presented. A comparison, in terms ...
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FLIP-Q: A QCIF resolution focal-plane array for low-power image processing
(Institute of Electrical and Electronics Engineers, 2011)This paper reports a 176×144-pixel smart image sensor designed and fabricated in a 0.35 CMOS-OPTO process. The chip ...
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Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs
(IEEE, 2021)The design of secure circuits in emerging technologies is an appealing area that requires new efforts and attention as an ...