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Ponencia
Exploring logic architectures suitable for TFETs devices
(Institute of Electrical and Electronics Engineers, 2017)
Tunnel transistors are steep subthreshold slope devices suitable for low voltage operation so being potential candidates to overcome the power density and energy inefficiency limitations of CMOS technology, which are ...
Ponencia
Assessing application areas for tunnel transistor technologies
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this ...
Artículo
Insights Into the Operation of Hyper-FET-Based Circuits
(Institute of Electrical and Electronics Engineers, 2017)
Devices combining transistors and phase transition materials are being investigated to obtain steep switching and a boost in the ION/IOFF ratio and, thus, to solve power and energy limitations of CMOS technologies. This ...
Artículo
Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas
(Institute of Electrical and Electronics Engineers, 2016)
In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than ...