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Ponencia
Exploring logic architectures suitable for TFETs devices
(Institute of Electrical and Electronics Engineers, 2017)
Tunnel transistors are steep subthreshold slope devices suitable for low voltage operation so being potential candidates to overcome the power density and energy inefficiency limitations of CMOS technology, which are ...
Ponencia
Complementary tunnel gate topology to reduce crosstalk effects
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. There are design challenges ...
Artículo
Insights Into the Operation of Hyper-FET-Based Circuits
(Institute of Electrical and Electronics Engineers, 2017)
Devices combining transistors and phase transition materials are being investigated to obtain steep switching and a boost in the ION/IOFF ratio and, thus, to solve power and energy limitations of CMOS technologies. This ...