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Mostrando ítems 1-10 de 62
Artículo
Efficient state reduction methods for PLA-based sequential circuits
(Institute of Electrical and Electronics Engineers, 1992)
Experiences with heuristics for the state reduction of finite-state machines are presented and two new heuristic algorithms described in detail. Results on machines from the literature and from the MCNC benchmark set are ...
Artículo
New analogue switch circuit having very low forward resistance
(Institution of Engineering and Technology, 1984)
A new circuit realisation for an analogue switch is reported. The main feature of the proposed design is the low value of the forward resistance as compared with commercial switches. Experimental data confirming the ...
Artículo
Impact of random channel mismatch on the SNR and SFDR of time-interleaved ADCs
(Institute of Electrical and Electronics Engineers, 2004)
Using several ADCs (Analog to Digital Converters) in parallel with convenient time offsets is considered as an efficient way to push the speed limits of data acquisition systems. However, a serious drawback of this ...
Ponencia
Analog neural networks for real-time constrained optimization
(Institute of Electrical and Electronics Engineers, 1990)
Architectures and circuit techniques for implementing general piecewise constrained optimization problems using VLSI techniques are explored. Discrete-time analog techniques are considered due to their inherent accuracy, ...
Artículo
On the Design of Voltage-Controlled Sinusoidal Oscillators Using OTA's
(Institute of Electrical and Electronics Engineers, 1990)
A unified systematic approach to the design of voltage-controlled oscillators using only operational transconductance amplifiers (OTA's) and capacitors is discussed in this paper. Two classical oscillator models, i.e., ...
Ponencia
Modeling OpAmp-induced harmonic distortion for switched-capacitor ΣΔ modulator design
(Institute of Electrical and Electronics Engineers, 1994)
This communication reports a new modeling of opamp-induced harmonic distortion in SC ΣΔ modulators, which is aimed to optimum design of this kind of circuit for high-performance applications. We analyze incomplete transfer ...
Ponencia
Architectures and building blocks for CMOS VLSI analog "neural" programmable optimizers
(Institute of Electrical and Electronics Engineers, 1992)
A modular reconfigurable serial architecture is presented for the analog/digital implementation of constrained optimization algorithms with digital programmability of the problem weights. Area overhead due to programmability ...
Artículo
10mhz cmos ota-c voltage-controlled quadrature oscillator
(Institution of Engineering and Technology, 1989)
A quadrature-type voltage-controlled oscillator with operational transconductance amplifiers and capacitors (OTA-C) is presented. A monolithic integrated CMOS test circuit is introduced to verify theoretical results. The ...
Ponencia
Analog integrated neural-like circuits for nonlinear programming
(Institute of Electrical and Electronics Engineers, 1989)
A systematic approach for the design of analog neural nonlinear programming solvers using switched-capacitor (SC) integrated circuit techniques is presented. The method is based on formulating a dynamic gradient system ...
Ponencia
A Tool for automated design of sigma-delta modulators using statistical optimization
(Institute of Electrical and Electronics Engineers, 1993)
A tool is presented which starting from high level specifications of SC σδ modulators (resolution, bandwidth and oversampling ratio) calculates first optimum specifications for the building blocks (op-amps, comparator, ...