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Mostrando ítems 1-10 de 27
Artículo
Efficient state reduction methods for PLA-based sequential circuits
(Institute of Electrical and Electronics Engineers, 1992)
Experiences with heuristics for the state reduction of finite-state machines are presented and two new heuristic algorithms described in detail. Results on machines from the literature and from the MCNC benchmark set are ...
Artículo
Reducing the Impact of Reverse Currents in Tunnel FET Rectifiers for Energy Harvesting Applications
(Institute of Electrical and Electronics Engineers, 2017)
RF to DC passive rectifiers can benefit from the superior performance at low voltage of tunnel transistors. They have shown higher power conversion efficiency (PCE) at low input power than Si FinFETs counterparts. In this ...
Artículo
nu MOS-based sorter for arithmetic applications
(Hindawi Publishing Corporation, 2000)
The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing some arithmetic demonstrators. In particular, both an (8×8)-multiplier and a (15,4) counter which use a ...
Ponencia
Using multi-threshold threshold gates in rtd-based logic design. A case study
(Laboratoire TIMA, 2007)
The basic building blocks for Resonant Tunnelling Diode (RTD) logic circuits are Threshold Gates (TGs) instead of the conventional Boolean gates (AND, OR, NAND, NOR) due to the fact that, when designing with RTDs, ...
Artículo
Domino inspired MOBILE networks
(Institute of Electrical and Electronics Engineers, 2012)
MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly chained, a four-phase clock scheme is required. A single phase scheme has been recently reported ...
Ponencia
DOE based high-performance gate-level pipelines
(Institute of Electrical and Electronics Engineers, 2014)
Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that in addition to the functional limitation associated to the noninverting behavior of domino gates, there ...
Ponencia
Exploring logic architectures suitable for TFETs devices
(Institute of Electrical and Electronics Engineers, 2017)
Tunnel transistors are steep subthreshold slope devices suitable for low voltage operation so being potential candidates to overcome the power density and energy inefficiency limitations of CMOS technology, which are ...
Artículo
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements
(Institute of Electrical and Electronics Engineers, 2014)
Abstract: Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable (MOBILE) gates are very suitable for implementing gate-level pipelines, which can be achieved without ...
Ponencia
Complementary tunnel gate topology to reduce crosstalk effects
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. There are design challenges ...
Artículo
RTD-CMOS pipelined networks for reduced power consumption
(Institute of Electrical and Electronics Engineers, 2011)
The incorporation of resonant tunneling diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance, producing higher circuit speed, reduced component count, and/or lower power consumption. ...