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Ponencia
Reconfiguration of Cascade ΣΔ Modulators for Multistandard GSM/Bluetooth/UIMTS/WLAN Transceivers
(Institute of Electrical and Electronics Engineers, 2006)
This paper presents design considerations for cascade Sigma-Delta Modulators (ΣΔMs) included in multi-standard wireless transceivers. Four different standards are covered: GSM, Bluetooth, UMTS and WLAN. A top-down design ...
Ponencia
MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time Sigma-Delta Modulators
(Institute of Electrical and Electronics Engineers, 2004)
This paper describes a tool that combines an accurate SIMULINK-based time-domain behavioural simulator with a statistical optimizer for the automated high-level synthesis of ΣΔ Modulators (ΣΔMs). The combination of high ...
Ponencia
An Optimization-based Tool for the High-Level Synthesis of Discrete-time and continuous-Time Sigma-Delta Modulators in the MATLAB/SIMULINK Environment
(Institute of Electrical and Electronics Engineers, 2004)
This paper presents a MATLAB toolbox for the automated high-level sizing of ΣΔ Modulators (ΣΔMs) based on the combination of an accurate time-domain behavioural simulator and a statistical optimizer. The implementation on ...
Ponencia
A Direct Synthesis Method of Cascaded Continuous-Time Sigma-Delta Modulators
(2005)
This paper presents an efficient method to synthesize cascaded sigma-delta modulators implemented with continuous-time circuits. It is based on the direct synthesis of the whole cascaded architecture in the continuous-time ...
Ponencia
An Alternative DfT Methodology to Test High-Resolution ΣΔ Modulators
(Institute of Electrical and Electronics Engineers, 2004)
In this paper, a novel DfT methodology to test high-resolution ΣΔ Modulators (ΣΔM) is introduced. The aim of the proposal is to reduce the test time required by conventional methodologies without degrading the accuracy of ...
Ponencia
Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time ΣΔ Modulator
(Institute of Electrical and Electronics Engineers, 2006)
This paper presents the design of a continuous- time multibit cascade 2-2-1 ΣΔ modulator for broadband telecom systems. The modulator architecture has been synthesized directly in the continuous-time domain instead of using ...
Capítulo de Libro
Tools for Automated Design of ΣΔ Modulators
(Springer, 1997)
We present a set of CAD tools to design ΣΔ modulators. They use statistical optimization to calculate optimum specifications for the building blocks used in the modulators, and optimum sizes for the components in these ...
Ponencia
A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator
(Institute of Electrical and Electronics Engineers, 2007)
This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade ΣΔ modulator. The modulator topology, directly synthesized in the continuous-time domain, consists of a third-order stage followed by ...