dc.creator | Domínguez Castro, Rafael | es |
dc.creator | Espejo Meana, Servando Carlos | es |
dc.creator | Rodríguez Vázquez, Ángel Benito | es |
dc.creator | Carmona Galán, Ricardo | es |
dc.creator | Földesy, Péter | es |
dc.creator | Zarándy, Ákos | es |
dc.creator | Szolgay, Péter | es |
dc.creator | Szirányi, Tamás | es |
dc.creator | Roska, Tamás | es |
dc.date.accessioned | 2020-03-19T16:27:46Z | |
dc.date.available | 2020-03-19T16:27:46Z | |
dc.date.issued | 1997 | |
dc.identifier.citation | Domínguez Castro, R., Espejo Meana, S.C., Rodríguez Vázquez, Á.B., Carmona Galán, R., Földesy, P., Zarándy, Á.,...,Roska, T. (1997). A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage. IEEE Journal of Solid-State Circuits, 32 (7), 1013-1026. | |
dc.identifier.issn | 0018-9200 | es |
dc.identifier.issn | 1558-173X | es |
dc.identifier.uri | https://hdl.handle.net/11441/94340 | |
dc.description.abstract | This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) binary images. Its processing function is determined by a reduced set of 19 analog coefficients whose values are programmable with 7-b accuracy. The internal programming signals are analog, but the external control interface is fully digital. Onchip nonlinear digital-to-analog converters (DAC's) map digitally coded weight values into analog control signals, using feedback to predistort their transfer characteristics in accordance to the response of the analog programming circuitry. This strategy cancels out the nonlinear dependence of the analog circuitry with the programming signal and reduces the influence of interchip technological parameters random fluctuations. The chip includes a small digital RAM memory to store eight sets of processing parameters in the periphery of the cell array and four 2-D binary images spatially distributed over the processing array. It also includes the necessary control circuitry to realize the stored instructions in any order and also to realize programmable logic operations among images. The chip architecture is based on the cellular neural/nonlinear network universal machine (CNN-UM). It has been fabricated in a 0.8-μm single-poly double-metal technology and features 2-μs operation speed (time required to process an image) and around 7-b accuracy in the analog processing operations. | es |
dc.description.sponsorship | Comisión Interministerial de Ciencia y Tecnología TIC96-1392-C02-02 | es |
dc.format | application/pdf | es |
dc.format.extent | 14 p. | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | IEEE Journal of Solid-State Circuits, 32 (7), 1013-1026. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Analog array processors | es |
dc.subject | Cellular neural networks | es |
dc.subject | Focal plane processors | es |
dc.subject | Vision chips | es |
dc.title | A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | TIC96-1392-C02-02 | es |
dc.relation.publisherversion | https://doi.org/10.1109/4.597292 | es |
dc.identifier.doi | 10.1109/4.597292 | es |
dc.journaltitle | IEEE Journal of Solid-State Circuits | es |
dc.publication.volumen | 32 | es |
dc.publication.issue | 7 | es |
dc.publication.initialPage | 1013 | es |
dc.publication.endPage | 1026 | es |
dc.identifier.sisius | 6702733 | es |