dc.creator | Medeiro Hidalgo, Fernando | es |
dc.creator | Pérez Verdú, Belén | es |
dc.creator | Rodríguez Vázquez, Ángel Benito | es |
dc.date.accessioned | 2020-03-19T16:12:55Z | |
dc.date.available | 2020-03-19T16:12:55Z | |
dc.date.issued | 1999 | |
dc.identifier.citation | Medeiro Hidalgo, F., Pérez Verdú, B. y Rodríguez Vázquez, Á.B. (1999). A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology. IEEE Journal of Solid-State Circuits, 34 (6), 748-760. | |
dc.identifier.issn | 0018-9200 | es |
dc.identifier.issn | 1558-173X | es |
dc.identifier.uri | https://hdl.handle.net/11441/94338 | |
dc.description.abstract | This paper presents a CMOS 0.7-μm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, and has a power consumption of 55 mW. Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth-order shaping function has been realized using a cascade architecture with three stages; the first stage is a second-order modulator, while the others are first-order modulators - referred to as a 2-1-1mb architecture. The quantizer of the last stage is 3 bits, while the other quantizers are single bit. The modulator architecture and coefficients have been optimized for reduced sensitivity to the errors in the 3-bit quantization process. Specifically, the 3-bit digital-to-analog converter tolerates 2.8% FS nonlinearity without significant degradation of the modulator performance. This makes the use of digital calibration unnecessary, which is a key point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures. On the other hand, as compared to a 2-1-1single-bit modulator previously designed for a mixed-signal asymmetrical digital subscriber line modem in the same technology, the modulator in this paper obtains one more bit resolution, enhances the operating frequency by a factor of two, and reduces the power consumption by a factor of four. | es |
dc.description.sponsorship | Comisión Interministerial de Ciencia y Tecnología TIC97-0580 | es |
dc.description.sponsorship | European Commission ESPRIT 8795 | es |
dc.format | application/pdf | es |
dc.format.extent | 13 p. | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | IEEE Journal of Solid-State Circuits, 34 (6), 748-760. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Analog-to-digital conversion | es |
dc.subject | Sigma–delta modulation | es |
dc.subject | Switched-capacitor circuits | es |
dc.title | A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | TIC97-0580 | es |
dc.relation.projectID | ESPRIT 8795 | es |
dc.relation.publisherversion | https://doi.org/10.1109/4.766809 | es |
dc.identifier.doi | 10.1109/4.766809 | es |
dc.journaltitle | IEEE Journal of Solid-State Circuits | es |
dc.publication.volumen | 34 | es |
dc.publication.issue | 6 | es |
dc.publication.initialPage | 748 | es |
dc.publication.endPage | 760 | es |
dc.identifier.sisius | 6702730 | es |