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dc.creatorMedeiro Hidalgo, Fernandoes
dc.creatorPérez Verdú, Belénes
dc.creatorRodríguez Vázquez, Ángel Benitoes
dc.date.accessioned2020-03-19T16:12:55Z
dc.date.available2020-03-19T16:12:55Z
dc.date.issued1999
dc.identifier.citationMedeiro Hidalgo, F., Pérez Verdú, B. y Rodríguez Vázquez, Á.B. (1999). A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology. IEEE Journal of Solid-State Circuits, 34 (6), 748-760.
dc.identifier.issn0018-9200es
dc.identifier.issn1558-173Xes
dc.identifier.urihttps://hdl.handle.net/11441/94338
dc.description.abstractThis paper presents a CMOS 0.7-μm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, and has a power consumption of 55 mW. Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth-order shaping function has been realized using a cascade architecture with three stages; the first stage is a second-order modulator, while the others are first-order modulators - referred to as a 2-1-1mb architecture. The quantizer of the last stage is 3 bits, while the other quantizers are single bit. The modulator architecture and coefficients have been optimized for reduced sensitivity to the errors in the 3-bit quantization process. Specifically, the 3-bit digital-to-analog converter tolerates 2.8% FS nonlinearity without significant degradation of the modulator performance. This makes the use of digital calibration unnecessary, which is a key point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures. On the other hand, as compared to a 2-1-1single-bit modulator previously designed for a mixed-signal asymmetrical digital subscriber line modem in the same technology, the modulator in this paper obtains one more bit resolution, enhances the operating frequency by a factor of two, and reduces the power consumption by a factor of four.es
dc.description.sponsorshipComisión Interministerial de Ciencia y Tecnología TIC97-0580es
dc.description.sponsorshipEuropean Commission ESPRIT 8795es
dc.formatapplication/pdfes
dc.format.extent13 p.es
dc.language.isoenges
dc.publisherInstitute of Electrical and Electronics Engineerses
dc.relation.ispartofIEEE Journal of Solid-State Circuits, 34 (6), 748-760.
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectAnalog-to-digital conversiones
dc.subjectSigma–delta modulationes
dc.subjectSwitched-capacitor circuitses
dc.titleA 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technologyes
dc.typeinfo:eu-repo/semantics/articlees
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.projectIDTIC97-0580es
dc.relation.projectIDESPRIT 8795es
dc.relation.publisherversionhttps://doi.org/10.1109/4.766809es
dc.identifier.doi10.1109/4.766809es
dc.journaltitleIEEE Journal of Solid-State Circuitses
dc.publication.volumen34es
dc.publication.issue6es
dc.publication.initialPage748es
dc.publication.endPage760es
dc.identifier.sisius6702730es

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Attribution-NonCommercial-NoDerivatives 4.0 Internacional
Except where otherwise noted, this item's license is described as: Attribution-NonCommercial-NoDerivatives 4.0 Internacional