dc.creator | Liu, Bo | es |
dc.creator | Fernández Fernández, Francisco Vidal | es |
dc.creator | Gielen, Georges | es |
dc.date.accessioned | 2018-07-05T14:37:18Z | |
dc.date.available | 2018-07-05T14:37:18Z | |
dc.date.issued | 2011 | |
dc.identifier.citation | Liu, B., Fernández Fernández, F.V. y Gielen, G. (2011). Efficient and accurate statistical analog yield optimization and variation-aware circuit sizing based on computational intelligence techniques. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30 (6), 793-805. | |
dc.identifier.issn | 0278-0070 | es |
dc.identifier.uri | https://hdl.handle.net/11441/76940 | |
dc.description.abstract | In nanometer complementary metal-oxide-semiconductor technologies, worst-case design methods and response-surface-based yield optimization methods face challenges in accuracy. Monte-Carlo (MC) simulation is general and accurate for yield estimation, but its efficiency is not high enough to make MC-based analog yield optimization, which requires many yield estimations, practical. In this paper, techniques inspired by computational intelligence are used to speed up yield optimization without sacrificing accuracy. A new sampling-based yield optimization approach, which determines the device sizes to optimize yield, is presented, called the ordinal optimization (OO)-based random-scale differential evolution (ORDE) algorithm. By proposing a two-stage estimation flow and introducing the OO technique in the first stage, sufficient samples are allocated to promising solutions, and repeated MC simulations of non-critical solutions are avoided. By the proposed evolutionary algorithm that uses differential evolution for global search and a random-scale mutation operator for fine tunings, the convergence speed of the yield optimization can be enhanced significantly. With the same accuracy, the resulting ORDE algorithm can achieve approximately a tenfold improvement in computational effort compared to an improved MC-based yield optimization algorithm integrating the infeasible sampling and Latin-hypercube sampling techniques. Furthermore, ORDE is extended from plain yield optimization to process-variation-aware single-objective circuit sizing. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30 (6), 793-805. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Yield optimization | es |
dc.subject | Variation-aware analog sizing | es |
dc.subject | Ordinal optimization | es |
dc.subject | Differential evolution | es |
dc.title | Efficient and accurate statistical analog yield optimization and variation-aware circuit sizing based on computational intelligence techniques | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.publisherversion | http://dx.doi.org/10.1109/TCAD.2011.2106850 | es |
dc.identifier.doi | 10.1109/TCAD.2011.2106850 | es |
idus.format.extent | 14 p. | es |
dc.journaltitle | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | es |
dc.publication.volumen | 30 | es |
dc.publication.issue | 6 | es |
dc.publication.initialPage | 793 | es |
dc.publication.endPage | 805 | es |