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dc.creatorLinares Barranco, Bernabées
dc.creatorSánchez Sinencio, Edgares
dc.creatorRodríguez Vázquez, Ángel Benitoes
dc.creatorHuertas Díaz, José Luises
dc.date.accessioned2018-06-29T13:15:42Z
dc.date.available2018-06-29T13:15:42Z
dc.date.issued1992
dc.identifier.citationLinares Barranco, B., Sánchez Sinencio, E., Rodríguez Vázquez, Á.B. y Huertas Díaz, J.L. (1992). A modular T-mode design approach for analog neural network hardware implementations. IEEE Journal of Solid-State Circuits, 27 (5), 701-713.
dc.identifier.issn0018-9200es
dc.identifier.urihttps://hdl.handle.net/11441/76572
dc.description.abstractA modular transconductance-mode (T-mode) design approach is presented for analog hardware implementations of neural networks. This design approach is used to build a modular bidirectional associative memory network. The authors show that the size of the whole system can be increased by interconnecting more modular chips. It is also shown that by changing the interconnection strategy different neural network systems can be implemented, such as a Hopfield network, a winner-take-all network, a simplified ART1 network, or a constrained optimization network. Experimentally measured results from CMOS 2-μm double-metal, double-polysilicon prototypes (MOSIS) are presented.es
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherInstitute of Electrical and Electronics Engineerses
dc.relation.ispartofIEEE Journal of Solid-State Circuits, 27 (5), 701-713.
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.titleA modular T-mode design approach for analog neural network hardware implementationses
dc.typeinfo:eu-repo/semantics/articlees
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.publisherversionhttp://dx.doi.org/10.1109/4.133157es
dc.identifier.doi10.1109/4.133157es
idus.format.extent13 p.es
dc.journaltitleIEEE Journal of Solid-State Circuitses
dc.publication.volumen27es
dc.publication.issue5es
dc.publication.initialPage701es
dc.publication.endPage713es

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Attribution-NonCommercial-NoDerivatives 4.0 Internacional
Except where otherwise noted, this item's license is described as: Attribution-NonCommercial-NoDerivatives 4.0 Internacional