dc.creator | Avedillo de Juan, María José | es |
dc.creator | Quintana Toledo, José María | es |
dc.creator | Huertas Díaz, José Luis | es |
dc.date.accessioned | 2018-06-26T13:58:03Z | |
dc.date.available | 2018-06-26T13:58:03Z | |
dc.date.issued | 1994 | |
dc.identifier.citation | Avedillo de Juan, M.J., Quintana Toledo, J.M. y Huertas Díaz, J.L. (1994). State merging and state splitting via state assignment: a new FSM synthesis algorithm. IEE Proceedings Computers and Digital Techniques, 141 (4), 229-237. | |
dc.identifier.issn | 1350-2387 | es |
dc.identifier.uri | https://hdl.handle.net/11441/76480 | |
dc.description.abstract | The authors describe a state assignment algorithm for FSMs which produces an assignment of non-necessarily distinct, and eventually, incompletely specified codes. In this new approach, state-reduction and state assignment are dealt with concurrently, and a restricted state splitting technique is explored. The algorithm is particularly appropriate for machines with compatibility relations among its states because the potentials of state merging are exploited during the state assignment step. The input to SMAS, the program implementing the algorithm, is a symbolic cover of the FSM. The output is a Boolean representation of both next state and output functions suitable to minimise with ESPRESSO. The machines in the MCNC benchmark set are used to test the new algorithm and to compare it with a well known state assignment program. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | IEE Proceedings Computers and Digital Techniques, 141 (4), 229-237. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | FSM synthesis | es |
dc.subject | State assignment | es |
dc.subject | State reduction | es |
dc.subject | Design automation | es |
dc.title | State merging and state splitting via state assignment: a new FSM synthesis algorithm | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.publisherversion | http://dx.doi.org/10.1049/ip-cdt:19941228 | es |
dc.identifier.doi | 10.1049/ip-cdt:19941228 | es |
idus.format.extent | 9 p. | es |
dc.journaltitle | IEE Proceedings Computers and Digital Techniques | es |
dc.publication.volumen | 141 | es |
dc.publication.issue | 4 | es |
dc.publication.initialPage | 229 | es |
dc.publication.endPage | 237 | es |