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dc.creatorAvedillo de Juan, María Josées
dc.creatorQuintana Toledo, José Maríaes
dc.creatorHuertas Díaz, José Luises
dc.date.accessioned2018-06-26T13:58:03Z
dc.date.available2018-06-26T13:58:03Z
dc.date.issued1994
dc.identifier.citationAvedillo de Juan, M.J., Quintana Toledo, J.M. y Huertas Díaz, J.L. (1994). State merging and state splitting via state assignment: a new FSM synthesis algorithm. IEE Proceedings Computers and Digital Techniques, 141 (4), 229-237.
dc.identifier.issn1350-2387es
dc.identifier.urihttps://hdl.handle.net/11441/76480
dc.description.abstractThe authors describe a state assignment algorithm for FSMs which produces an assignment of non-necessarily distinct, and eventually, incompletely specified codes. In this new approach, state-reduction and state assignment are dealt with concurrently, and a restricted state splitting technique is explored. The algorithm is particularly appropriate for machines with compatibility relations among its states because the potentials of state merging are exploited during the state assignment step. The input to SMAS, the program implementing the algorithm, is a symbolic cover of the FSM. The output is a Boolean representation of both next state and output functions suitable to minimise with ESPRESSO. The machines in the MCNC benchmark set are used to test the new algorithm and to compare it with a well known state assignment program.es
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherInstitute of Electrical and Electronics Engineerses
dc.relation.ispartofIEE Proceedings Computers and Digital Techniques, 141 (4), 229-237.
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectFSM synthesises
dc.subjectState assignmentes
dc.subjectState reductiones
dc.subjectDesign automationes
dc.titleState merging and state splitting via state assignment: a new FSM synthesis algorithmes
dc.typeinfo:eu-repo/semantics/articlees
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.publisherversionhttp://dx.doi.org/10.1049/ip-cdt:19941228es
dc.identifier.doi10.1049/ip-cdt:19941228es
idus.format.extent9 p.es
dc.journaltitleIEE Proceedings Computers and Digital Techniqueses
dc.publication.volumen141es
dc.publication.issue4es
dc.publication.initialPage229es
dc.publication.endPage237es

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