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dc.creatorLinares Barranco, Bernabées
dc.creatorSerrano Gotarredona, María Teresaes
dc.creatorSerrano Gotarredona, Rafaeles
dc.date.accessioned2018-06-15T14:46:09Z
dc.date.available2018-06-15T14:46:09Z
dc.date.issued2003
dc.identifier.citationLinares Barranco, B., Serrano Gotarredona, M.T. y Serrano Gotarredona, R. (2003). Compact low-power calibration mini-DACs for neural arrays with programmable weights. IEEE Transactions on Neural Networks, 14 (5), 1207-1216.
dc.identifier.issn1045-9227es
dc.identifier.issn1941-0093es
dc.identifier.urihttps://hdl.handle.net/11441/76270
dc.description.abstractThis paper considers the viability of compact low-resolution low-power mini digital-to-analog converters (mini-DACs) for use in large arrays of neural type cells, where programmable weights are required. Transistors are biased in weak inversion in order to yield small currents and low power consumptions, a necessity when building large size arrays. One important drawback of weak inversion operation is poor matching between transistors. The resulting effective precision of a fabricated array of 50 DACs turned out to be 47% (1.1 bits), due to transistor mismatch. However, it is possible to combine them two by two in order to build calibrated DACs, thus compensating for inter-DAC mismatch. It is shown experimentally that the precision can be improved easily by a factor of 10 (4.8% or 4.4 bits), which makes these DACs viable for low-resolution applications such as massive arrays of neural processing circuits. A design methodology is provided, and illustrated through examples, to obtain calibrated mini-DACs of a given target precision. As an example application, we show simulation results of using this technique to calibrate an array of digitally controlled integrate-and-fire neurons.es
dc.description.sponsorshipGobierno de España TIC1999-0446-C02-02, TIC2000-0406-P4-05, FIT-07000/2002/921, TIC2002-10878-Ees
dc.description.sponsorshipEuropean Union IST- 2001-34124es
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherInstitute of Electrical and Electronics Engineerses
dc.relation.ispartofIEEE Transactions on Neural Networks, 14 (5), 1207-1216.
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectAnalog designes
dc.subjectCalibrationes
dc.subjectCurrent splitterses
dc.subjectDigital-to-analog converterses
dc.subjectFuzzy circuitses
dc.subjectNeural networkses
dc.subjectSubthresholdes
dc.subjectWeak inversiones
dc.titleCompact low-power calibration mini-DACs for neural arrays with programmable weightses
dc.typeinfo:eu-repo/semantics/articlees
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadoreses
dc.relation.projectIDTIC1999-0446-C02-02es
dc.relation.projectIDTIC2000-0406-P4-05es
dc.relation.projectIDFIT-07000/2002/921es
dc.relation.projectIDTIC2002-10878-Ees
dc.relation.projectIDIST- 2001-34124es
dc.relation.publisherversionhttp://dx.doi.org/10.1109/TNN.2003.816370es
dc.identifier.doi10.1109/TNN.2003.816370es
idus.format.extent10 p.es
dc.journaltitleIEEE Transactions on Neural Networkses
dc.publication.volumen14es
dc.publication.issue5es
dc.publication.initialPage1207es
dc.publication.endPage1216es
dc.contributor.funderGobierno de España
dc.contributor.funderEuropean Union (UE)

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