On algorithmic rate-coded AER generation
|Author||Linares Barranco, Alejandro
Jiménez Moreno, Gabriel
Linares Barranco, Bernabé
Civit Balcells, Antón
|Department||Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores|
|Abstract||This paper addresses the problem of converting a conventional video stream based on sequences of frames into the spike event-based representation known as the address-event-representation (AER). In this paper we concentrate ...
This paper addresses the problem of converting a conventional video stream based on sequences of frames into the spike event-based representation known as the address-event-representation (AER). In this paper we concentrate on rate-coded AER. The problem is addressed as an algorithmic problem, in which different methods are proposed, implemented and tested through software algorithms. The proposed algorithms are comparatively evaluated according to different criteria. Emphasis is put on the potential of such algorithms for a) doing the frame-based to event-based representation in real time, and b) that the resulting event streams ressemble as much as possible those generated naturally by rate-coded address-event VLSI chips, such as silicon AER retinae. It is found that simple and straightforward algorithms tend to have high potential for real time but produce event distributions that differ considerably from those obtained in AER VLSI chips. On the other hand, sophisticated algorithms that yield better event distributions are not efficient for real time operations. The methods based on linear-feedback-shift-register (LFSR) pseudorandom number generation is a good compromise, which is feasible for real time and yield reasonably well distributed events in time. Our software experiments, on a 1.6-GHz Pentium IV, show that at 50% AER bus load the proposed algorithms require between 0.011 and 1.14 ms per 8 bit-pixel per frame. One of the proposed LFSR methods is implemented in real time hardware using a prototyping board that includes a VirtexE 300 FPGA. The demonstration hardware is capable of transforming frames of 64 times; 64 pixels of 8-bit depth at a frame rate of 25 frames per second, producing spike events at a peak rate of 107 events per second.
|Funding agencies||European Union (UE)
Gobierno de España
|Citation||Linares Barranco, A., Jiménez Moreno, G., Linares Barranco, B. y Civit Balcells, A. (2006). On algorithmic rate-coded AER generation. IEEE Transactions on Neural Networks, 17 (3), 771-788.|