dc.creator | García Sánchez, Gerardo | es |
dc.creator | Rosa Utrera, José Manuel de la | es |
dc.date.accessioned | 2018-05-15T13:33:05Z | |
dc.date.available | 2018-05-15T13:33:05Z | |
dc.date.issued | 2014 | |
dc.identifier.citation | García Sánchez, G. y Rosa Utrera, J.M.d.L. (2014). Efficient Hybrid Continuous-Time/Discrete-Time Cascade Modulators for Wideband Applications. Microelectronics Journal, 45 (10), 1234-1246. | |
dc.identifier.issn | 0026-2692 | es |
dc.identifier.uri | https://hdl.handle.net/11441/74633 | |
dc.description.abstract | This paper analyses the use of hybrid continuous-time/discrete-time cascade ΣΔ modulators for the implementation of power-efficient analog-to-digital converters in broadband wireless communication systems. Two alternative implementations of multi-rate cascade architectures are studied and compared with conventional single-rate continuous-time topologies, taking into account the impact of main circuit-level error mechanisms, namely: mismatch, finite dc gain and gain-bandwidth product. In all cases, closed-form design equations are derived for the nonideal in-band noise power of all ΣΔ modulators under study, providing analytical relationships between their system-level performance and the corresponding circuit-level error parameters. Theoretical predictions match simulation results, showing that the lowest performance degradation is obtained by a new kind of multi-rate hybrid ΣΔ modulator, in which the front-end (continuous-time) stage operates at a higher rate than the back-end (discrete-time) stages. As a case study, the design of a hybrid GmC/switched-capacitor fourth-order (two-stage, 4-bit) cascade ΣΔ modulator is discussed to illustrate the potential benefits of the presented approach | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2010-14825/MIC | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Elsevier | es |
dc.relation.ispartof | Microelectronics Journal, 45 (10), 1234-1246. | |
dc.rights | Atribución-NoComercial-SinDerivadas 3.0 Estados Unidos de América | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Analog-to-digital converters | es |
dc.subject | Sigma-delta modulators | es |
dc.subject | Hybrid continuous-time/discrete-time | es |
dc.subject | Multi-rate signal processing | es |
dc.subject | Sigma-delta modulators | es |
dc.title | Efficient Hybrid Continuous-Time/Discrete-Time Cascade Modulators for Wideband Applications | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.relation.projectID | TEC2010-14825/MIC | es |
dc.relation.publisherversion | http://dx.doi.org/10.1016/j.mejo.2013.10.017 | es |
dc.identifier.doi | 10.1016/j.mejo.2013.10.017 | es |
idus.format.extent | 33 p. | es |
dc.journaltitle | Microelectronics Journal | es |
dc.publication.volumen | 45 | es |
dc.publication.issue | 10 | es |
dc.publication.initialPage | 1234 | es |
dc.publication.endPage | 1246 | es |
dc.contributor.funder | Ministerio de Economía y Competitividad (MINECO). España | |