Mostrar el registro sencillo del ítem
Artículo
Semi-empirical RF MOST model for CMOS 65 nm technologies: theory, extraction method and validation
dc.creator | Fiorelli, Rafaella | es |
dc.creator | Peralías Macías, Eduardo | es |
dc.date.accessioned | 2018-05-08T13:42:56Z | |
dc.date.available | 2018-05-08T13:42:56Z | |
dc.date.issued | 2016 | |
dc.identifier.citation | Fiorelli, R. y Peralías Macías, E. (2016). Semi-empirical RF MOST model for CMOS 65 nm technologies: theory, extraction method and validation. Integration: The VLSI Journal, 52, 228-236. | |
dc.identifier.issn | 0167-9260 | es |
dc.identifier.uri | https://hdl.handle.net/11441/74308 | |
dc.description.abstract | This paper presents a simple but accurate semi-empirical model especially focused on 65 nm MOST (MOS transistor) technologies and radio-frequency (RF) applications. It is obtained by means of simple dc and noise simulations extracted over a constrained set of MOSTs. The fundamental variable of the model is the MOST transconductance to current drain ratio gm/ID. Specifically it comprises the large signal DC normalized current, all conductances and transconductances and the normalized intrinsic capacitances. As well, noise MOST characteristics of flicker noise, white noise and MOST corner frequency description are provided. To validate the referred model the widely utilized cascoded common source low noise amplifier (CS-LNA), in 2.5 GHz and 5.3 GHz RF applications is picked. For the presented set of designs different gm/ID ratios are considered. Finally, the computed results are assessed by comparing with the outcomes of electrical simulations. | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2011-28302 | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Elsevier | es |
dc.relation.ispartof | Integration: The VLSI Journal, 52, 228-236. | |
dc.rights | Atribución-NoComercial-SinDerivadas 3.0 Estados Unidos de América | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | MOS transistor | es |
dc.subject | gm/ID | es |
dc.subject | Semi-empirical | es |
dc.subject | RF | es |
dc.subject | Nanometer technology | es |
dc.subject | 65 nm CMOS | es |
dc.subject | Inversion level | es |
dc.subject | CS-LNA | es |
dc.title | Semi-empirical RF MOST model for CMOS 65 nm technologies: theory, extraction method and validation | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.relation.projectID | TEC2011-28302 | es |
dc.relation.publisherversion | http://dx.doi.org/10.1016/j.vlsi.2015.07.018 | es |
dc.identifier.doi | 10.1016/j.vlsi.2015.07.018 | es |
idus.format.extent | 12 p. | es |
dc.journaltitle | Integration: The VLSI Journal | es |
dc.publication.volumen | 52 | es |
dc.publication.initialPage | 228 | es |
dc.publication.endPage | 236 | es |
dc.contributor.funder | Ministerio de Economía y Competitividad (MINECO). España |
Ficheros | Tamaño | Formato | Ver | Descripción |
---|---|---|---|---|
Semi-empirical RF MOST model.pdf | 3.490Mb | ![]() | Ver/ | |