dc.creator | Núñez Martínez, Juan | es |
dc.creator | Avedillo de Juan, María José | es |
dc.creator | Quintana Toledo, José María | es |
dc.date.accessioned | 2018-04-12T16:17:50Z | |
dc.date.available | 2018-04-12T16:17:50Z | |
dc.date.issued | 2014 | |
dc.identifier.citation | Nuñez Martínez, J., Avedillo de Juan, M.J. y Quintana Toledo, J.M. (2014). Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22 (10), 2238-2242. | |
dc.identifier.issn | 1063-8210 | es |
dc.identifier.uri | https://hdl.handle.net/11441/72620 | |
dc.description.abstract | Abstract: Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable (MOBILE) gates are very suitable for implementing gate-level pipelines, which can be achieved without resorting to memory elements. The MOBILE operating principle is implemented operating two series connected negative differential resistance devices with a clock bias. This brief describes and experimentally validates a two-phase clock scheme for such MOBILE-based ultragrained pipelines. Its advantages over other reported interconnection schemes for MOBILE gates, and also over pure CMOS two-phase counterparts, are stated and analyzed. Chains of MOBILE gates have been fabricated and the experimental results of their correct operation with a two-phase clock scheme are provided. As far as we know, this is the first working MOBILE circuit to have been reported with this interconnection architecture. | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2010-18937 | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22 (10), 2238-2242. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Monostable-to-Bistable Logic Element | es |
dc.subject | Negative Differential Resistance | es |
dc.subject | Pipeline | es |
dc.subject | Clock schemes | es |
dc.title | Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | TEC2010-18937 | es |
dc.relation.publisherversion | https://doi.org/10.1109/TVLSI.2013.2283306 | es |
dc.identifier.doi | 10.1109/TVLSI.2013.2283306 | es |
idus.format.extent | 5 p. | es |
dc.journaltitle | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | es |
dc.publication.volumen | 22 | es |
dc.publication.issue | 10 | es |
dc.publication.initialPage | 2238 | es |
dc.publication.endPage | 2242 | es |
dc.contributor.funder | Ministerio de Economía y Competitividad (MINECO). España | |