Ponencia
Digital implementation of hierarchical piecewise-affine controllers
Autor/es | Baturone Castillo, María Iluminada
Martínez Rodríguez, Macarena Cristina Brox Jiménez, Piedad Gersnoviez, A. Sánchez Solano, Santiago |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2011 |
Fecha de depósito | 2017-03-29 |
Publicado en |
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ISBN/ISSN | 978-1-4244-9310-4 |
Resumen | This paper proposes the design of hierarchical piecewise-affine (PWA) controllers to alleviate the processing time or prohibitive memory requirements of large controller structures. The constituent PWA modules of the ... This paper proposes the design of hierarchical piecewise-affine (PWA) controllers to alleviate the processing time or prohibitive memory requirements of large controller structures. The constituent PWA modules of the hierarchical solution have fewer inputs and/or coarser partitions, so that they can reduce considerably the hardware resources required and/or the time response of the controller. A design methodology aided by CAD tools is employed to design the parameters of the controller, implement its architecture in an FPGA, and verify the static and dynamic behavior of the digital implementation by applying hardware-in-the-loop testing. |
Identificador del proyecto | info:eu-repo/grantAgreement/EC/FP7/248858
TEC2008-04920 DPI2008-03847 P08-TIC-03674 |
Cita | Baturone Castillo, M.I., Martínez Rodríguez, M.C., Brox Jiménez, P., Gersnoviez, A. y Sánchez Solano, S. (2011). Digital implementation of hierarchical piecewise-affine controllers. En IEEE International Symposium on Industrial Electronics (ISIE) (1497-1502), Gdansk: Institute of Electrical and Electronics Engineers. |
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