dc.creator | Baturone Castillo, María Iluminada | es |
dc.creator | Sánchez Solano, Santiago | es |
dc.creator | Gersnoviez, A. | es |
dc.creator | Brox Jiménez, María | es |
dc.date.accessioned | 2017-03-24T14:22:49Z | |
dc.date.available | 2017-03-24T14:22:49Z | |
dc.date.issued | 2010 | |
dc.identifier.citation | Baturone Castillo, M.I., Sánchez Solano, S., Gersnoviez, A. y Brox Jiménez, M. (2010). An automated design flow from linguistic models to piecewise polynomial digital circuits. En IEEE International Symposium on Circuits and Systems (ISCAS) (3317-3320), París: Institute of Electrical and Electronics Engineers. | |
dc.identifier.isbn | 978-1-4244-5308-5 | es |
dc.identifier.uri | http://hdl.handle.net/11441/56250 | |
dc.description.abstract | This paper describes how the different CAD tools of the environment Xfuzzy 3, developed in Microelectronics Institute of Seville and University of Seville, allow to translate expressive linguistic models into mathematical ones, in particular, into a combination of piecewise polynomial systems that can be implemented efficiently in hardware. The new synthesis tool of Xfuzzy 3 automates communication with Xilinx System Generator in Matlab, thus facilitating implementation of the linguistic model into an FPGA from Xilinx. This is illustrated with the design of a navigation controller for an autonomous robot. | es |
dc.description.sponsorship | Comunidad Europea FP7-IST-248858 | es |
dc.description.sponsorship | Ministerio de Ciencia y Tecnología TEC2008-04920 | es |
dc.description.sponsorship | Junta de Andalucía P08-TIC-03674 | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | IEEE International Symposium on Circuits and Systems (ISCAS) (2010), pp. 3317-3320. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | An automated design flow from linguistic models to piecewise polynomial digital circuits | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | EC/FP7/248858 | es |
dc.relation.projectID | TEC2008-04920 | es |
dc.relation.projectID | P08-TIC-03674 | es |
dc.relation.publisherversion | https://doi.org/10.1109/ISCAS.2010.5537890 | es |
dc.identifier.doi | 10.1109/ISCAS.2010.5537890 | es |
idus.format.extent | 4 p. | es |
dc.publication.initialPage | 3317 | es |
dc.publication.endPage | 3320 | es |
dc.eventtitle | IEEE International Symposium on Circuits and Systems (ISCAS) | es |
dc.eventinstitution | París | es |