dc.creator | Viejo Cortés, Julián | es |
dc.creator | Villar de Ossorno, José Ignacio | es |
dc.creator | Juan Chico, Jorge | es |
dc.creator | Millán Calderón, Alejandro | es |
dc.creator | Bellido Díaz, Manuel Jesús | es |
dc.creator | Ostúa Arangüena, Enrique | es |
dc.date.accessioned | 2017-01-24T11:53:14Z | |
dc.date.available | 2017-01-24T11:53:14Z | |
dc.date.issued | 2010 | |
dc.identifier.citation | Viejo Cortés, J., Villar de Ossorno, J.I., Juan Chico, J., Millán Calderón, A., Bellido Díaz, M.J. y Ostúa Arangüena, E. (2010). Design and implementation of a suitable core for on-chip long-term verification. En International Symposium on Industrial Embedded Systems, SIES 2010 (234-237), Trento, Italia: IEEE Computer Society. | |
dc.identifier.isbn | 978-1-4244-5839-4 | es |
dc.identifier.uri | http://hdl.handle.net/11441/52637 | |
dc.description.abstract | Traditional on-chip and off-chip logic analyzers
present important shortcomings when used for the long-term
verification of industrial embedded systems, forcing the designer
to implement ad-hoc verification solutions. This contribution
presents a suitable solution for long-term verification of FPGAbased
designs consisting on a verification core that uses the
Picoblaze microcontroller, dedicated logic and a serial port
communication in order to monitor the internal signals of the
system in a continuous way. The core design focuses on low
resource requirements and reusability and has been successfully
applied to the verification of a real industrial synchronization
platform showing remarkable advantages over commercial onchip
solutions like Xilinx’s ChipScope Pro. | es |
dc.description.sponsorship | Ministerio de Educación y Cultura TEC2007-61802/MIC (HIPER | es |
dc.description.sponsorship | Ministerio de Educación y Cultura PROFIT-MITC SEPIC TSI-020100-2008-258 | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.relation.ispartof | International Symposium on Industrial Embedded Systems, SIES 2010 (2010), p 234-237 | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | Design and implementation of a suitable core for on-chip long-term verification | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.projectID | TEC2007-61802/MIC (HIPER | es |
dc.relation.projectID | PROFIT-MITC SEPIC TSI-020100-2008-258 | es |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/5551400/ | es |
dc.identifier.doi | 10.1109/SIES.2010.5551400 | es |
dc.contributor.group | Universidad de Sevilla. TIC204: Investigación y Desarrollo Digital (ID2) | es |
idus.format.extent | 4 | es |
dc.publication.initialPage | 234 | es |
dc.publication.endPage | 237 | es |
dc.eventtitle | International Symposium on Industrial Embedded Systems, SIES 2010 | es |
dc.eventinstitution | Trento, Italia | es |
dc.relation.publicationplace | USA | es |
dc.contributor.funder | Ministerio de Educación y Cultura (MEC). España | |