dc.creator | Acosta Jiménez, Antonio José | es |
dc.creator | Barriga Barros, Ángel | es |
dc.creator | Valencia Barrero, Manuel | es |
dc.creator | Bellido Díaz, Manuel Jesús | es |
dc.creator | Huertas Díaz, José Luis | es |
dc.date.accessioned | 2017-01-18T11:23:55Z | |
dc.date.available | 2017-01-18T11:23:55Z | |
dc.date.issued | 1993 | |
dc.identifier.citation | Acosta Jiménez, A.J., Barriga Barros, Á., Valencia Barrero, M., Bellido Díaz, M.J. y Huertas, J.L. (1993). Modeling of Real Bistables in VHDL. En Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference (460-465), Hamburg, Germany: IEEE Computer Society. | |
dc.identifier.isbn | 0-8186-4350-1 | es |
dc.identifier.uri | http://hdl.handle.net/11441/52416 | |
dc.description.abstract | A complete VHDL model of bistables including their
metastable operation is presented. An RS-NAND latch
has been modelled as a basic structure, orienting its
implementation towards its inclusion in a cell library.
Two applications are included: description of a more
complex latch (D-type) and description of a circuit containing
three latches where metastable signals are propagated.
Simulation results show that the presented niodel
provides very realistic information about the device
behavior, which until now had to be obtained through
electric simulation. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.relation.ispartof | Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference (1993), p 460-465 | |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | Modeling of Real Bistables in VHDL | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/publishedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/410677/?reload=true | es |
dc.identifier.doi | 10.1109/EURDAC.1993.410677 | es |
idus.format.extent | 6 | es |
dc.publication.initialPage | 460 | es |
dc.publication.endPage | 465 | es |
dc.eventtitle | Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference | es |
dc.eventinstitution | Hamburg, Germany | es |
dc.relation.publicationplace | USA | es |