dc.creator | Millán Calderón, Alejandro | es |
dc.creator | Viejo Cortés, Julián | es |
dc.creator | Quirós Carmona, Juan | es |
dc.creator | Bellido Díaz, Manuel Jesús | es |
dc.creator | Guerrero Martos, David | es |
dc.creator | Ostúa Arangüena, Enrique | es |
dc.date.accessioned | 2016-12-19T08:46:42Z | |
dc.date.available | 2016-12-19T08:46:42Z | |
dc.date.issued | 2016 | |
dc.identifier.citation | Millán Calderón, A., Viejo Cortés, J., Quiros, J., Bellido Díaz, M.J., Guerrero Martos, D. y Ostua Arangüena, E. (2016). Building a basic membrane computer. En BWMC 2016 : 14th Brainstorming Week on Membrane Computing : Sevilla, E. T. S. de Ingeniería Informática, February 1-5 (269-280), Sevilla: Fénix. | |
dc.identifier.uri | http://hdl.handle.net/11441/50686 | |
dc.description.abstract | In this work, we present the building of two well-known membrane com-
puters (squares generator and divisor test). Although they are very basic machines they
present problems common to every P system (competition, parallel execution of rules,
membrane dissolution, etc.) that have to be solved in order to get real emulations for
them. The presented designs mimic the systems operation in a realistic way, by achieving
both maximum parallelism and non-determinism, and demonstrating for the rst time
that a membrane computer can actually be built in silico. Our architectures fully emu-
late the membranes behaviour yielding to a performance of one transition per clock cycle,
supposing a real physical realization of the mentioned machines. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Fénix | es |
dc.relation.ispartof | BWMC 2016 : 14th Brainstorming Week on Membrane Computing : Sevilla, E. T. S. de Ingeniería Informática, February 1-5 (2016), p 269-280 | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Membrane computing | es |
dc.subject | P system | es |
dc.subject | digital circuit design | es |
dc.subject | parallel computing | es |
dc.subject | recon gurable hardware | es |
dc.subject | FPGA | es |
dc.title | Building a basic membrane computer | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dc.type.version | info:eu-repo/semantics/publishedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.publisherversion | http://www.gcn.us.es/files/14bwmc/269_main_building.pdf | es |
dc.contributor.group | Universidad de Sevilla, TIC204: Investigación y Desarrollo Digital | es |
idus.format.extent | 12 | es |
dc.publication.initialPage | 269 | es |
dc.publication.endPage | 280 | es |
dc.eventtitle | BWMC 2016 : 14th Brainstorming Week on Membrane Computing : Sevilla, E. T. S. de Ingeniería Informática, February 1-5 | es |
dc.eventinstitution | Sevilla | es |
dc.relation.publicationplace | Sevilla | es |