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New high performance second generation CMOS current conveyor

dc.creatorMarri, Swathi
dc.creatorRamírez Angulo, Jaime
dc.creatorLópez Martín, Antonio
dc.creatorGonzález Carvajal, Ramón
dc.date.accessioned2015-03-12T10:17:07Z
dc.date.available2015-03-12T10:17:07Z
dc.date.issued2009
dc.identifier.urihttp://hdl.handle.net/11441/23445
dc.description.abstractA new high performance second-generation CMOS current conveyor architecture is presented. It is built using a differential flipped voltage follower as its input buffer stage and a cascode current mirror as output stage. It is characterized by very low output impedance. It provides gain independent high bandwidth when used to implement a programmable gain voltage amplifier. Simulation and experimental results in AMI 0.5µm CMOS technology are provided to validate the characteristics of the design.es
dc.formatapplication/pdfes
dc.language.isoenges
dc.relation.ispartofXXIV Conference on Design of Circuits and Integrated Systems: Zaragoza, 18-20 de noviembre 2009es
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectAnalog integrated circuitses
dc.subjectCurrent mode signal processingen
dc.subjectCurrent conveyoren
dc.titleNew high performance second generation CMOS current conveyores
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.rights.accessRightsinfo:eu-repo/semantics/openAccess
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Ingeniería Electrónicaes
dc.identifier.idushttps://idus.us.es/xmlui/handle/11441/23445

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