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dc.creatorTena Sánchez, Ericaes
dc.creatorPotestad Ordóñez, Francisco Eugenioes
dc.creatorZúñiga González, Virginiaes
dc.creatorFernández García, Carloses
dc.creatorMora Gutiérrez, José Migueles
dc.creatorJiménez Fernández, Carlos Jesúses
dc.creatorAcosta Jiménez, Antonio Josées
dc.date.accessioned2024-07-08T10:53:39Z
dc.date.available2024-07-08T10:53:39Z
dc.date.issued2022
dc.identifier.isbn978-84-88734-13-6es
dc.identifier.urihttps://hdl.handle.net/11441/161172
dc.description.abstractIn this paper, we present a review of the work [1]. The fast settlement of Privacy and Secure operations in the Internet of Things (IoT) is appealing the selection of mechanisms to achieve a higher level of security at the minimum cost and with reasonable performances. In recent years, dozens of proposals have been presented to design circuits resistant to Power Analysis attacks. In this paper a deep review of the state of the art of gate-level countermeasures against Power Analysis attacks has been done, performing a comparison between hiding approaches (the power consumption is intended to be the same for all the data processed) and the ones considering a masking procedure (the data are masked and behave as random). The most relevant proposals in the literature, 35 for hiding and 6 for masking, have been analyzed, not only by using data provided by proposers, but also those included in other references for comparison.es
dc.formatapplication/pdfes
dc.format.extent2 p.es
dc.language.isoenges
dc.publisherFundación Tecnalia Research and Innovationes
dc.relation.ispartofInvestigación en Ciberseguridad. Actas de las VII Jornadas Nacionaleses
dc.rightsAtribución 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/*
dc.subjectHardware countermeasureses
dc.subjectGate leveles
dc.subjectVLSI design of cryptographic circuitses
dc.subjectSide-channel attacks (SCAs)es
dc.subjectInformation securityes
dc.subjectLogic designes
dc.subjectInternet of things (IoT)es
dc.titleReview of Gate-Level Hardware Countermeasure Comparison Against Power Analysis Attackses
dc.typeinfo:eu-repo/semantics/bookPartes
dc.type.versioninfo:eu-repo/semantics/publishedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Tecnología Electrónicaes
dc.relation.projectIDSCAROT 1380823es
dc.relation.projectIDEU H2020 952622es
dc.relation.projectIDPID2020-116664RB-I00es
dc.relation.publisherversionhttps://2022.jnic.es/es
dc.contributor.groupUniversidad de Sevilla. TIC180: Diseño de Circuitos Integrados Digitales y Mixtoses
dc.publication.initialPage290es
dc.publication.endPage291es
dc.contributor.funderUniversidad de Sevillaes
dc.contributor.funderJunta de Andalucíaes
dc.contributor.funderEuropean Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER)es
dc.contributor.funderEuropean Union (UE). H2020es
dc.contributor.funderMinisterio de Ciencia e Innovación (MICIN). Españaes

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