dc.creator | Tena Sánchez, Erica | es |
dc.creator | Potestad Ordóñez, Francisco Eugenio | es |
dc.creator | Zúñiga González, Virginia | es |
dc.creator | Fernández García, Carlos | es |
dc.creator | Mora Gutiérrez, José Miguel | es |
dc.creator | Jiménez Fernández, Carlos Jesús | es |
dc.creator | Acosta Jiménez, Antonio José | es |
dc.date.accessioned | 2024-07-08T10:53:39Z | |
dc.date.available | 2024-07-08T10:53:39Z | |
dc.date.issued | 2022 | |
dc.identifier.isbn | 978-84-88734-13-6 | es |
dc.identifier.uri | https://hdl.handle.net/11441/161172 | |
dc.description.abstract | In this paper, we present a review of the work [1].
The fast settlement of Privacy and Secure operations in the
Internet of Things (IoT) is appealing the selection of mechanisms
to achieve a higher level of security at the minimum cost and with
reasonable performances. In recent years, dozens of proposals
have been presented to design circuits resistant to Power Analysis
attacks. In this paper a deep review of the state of the art of
gate-level countermeasures against Power Analysis attacks has
been done, performing a comparison between hiding approaches
(the power consumption is intended to be the same for all the
data processed) and the ones considering a masking procedure
(the data are masked and behave as random). The most relevant
proposals in the literature, 35 for hiding and 6 for masking, have
been analyzed, not only by using data provided by proposers,
but also those included in other references for comparison. | es |
dc.format | application/pdf | es |
dc.format.extent | 2 p. | es |
dc.language.iso | eng | es |
dc.publisher | Fundación Tecnalia Research and Innovation | es |
dc.relation.ispartof | Investigación en Ciberseguridad. Actas de las VII Jornadas Nacionales | es |
dc.rights | Atribución 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by/4.0/ | * |
dc.subject | Hardware countermeasures | es |
dc.subject | Gate level | es |
dc.subject | VLSI design of cryptographic circuits | es |
dc.subject | Side-channel attacks (SCAs) | es |
dc.subject | Information security | es |
dc.subject | Logic design | es |
dc.subject | Internet of things (IoT) | es |
dc.title | Review of Gate-Level Hardware Countermeasure Comparison Against Power Analysis Attacks | es |
dc.type | info:eu-repo/semantics/bookPart | es |
dc.type.version | info:eu-repo/semantics/publishedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.projectID | SCAROT 1380823 | es |
dc.relation.projectID | EU H2020 952622 | es |
dc.relation.projectID | PID2020-116664RB-I00 | es |
dc.relation.publisherversion | https://2022.jnic.es/ | es |
dc.contributor.group | Universidad de Sevilla. TIC180: Diseño de Circuitos Integrados Digitales y Mixtos | es |
dc.publication.initialPage | 290 | es |
dc.publication.endPage | 291 | es |
dc.contributor.funder | Universidad de Sevilla | es |
dc.contributor.funder | Junta de Andalucía | es |
dc.contributor.funder | European Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER) | es |
dc.contributor.funder | European Union (UE). H2020 | es |
dc.contributor.funder | Ministerio de Ciencia e Innovación (MICIN). España | es |