dc.creator | Guerrero Martos, David | es |
dc.creator | Cano Quiveu, Germán | es |
dc.creator | Juan Chico, Jorge | es |
dc.creator | Millán Calderón, Alejandro | es |
dc.creator | Bellido Díaz, Manuel Jesús | es |
dc.creator | Viejo Cortés, Julián | es |
dc.creator | Ruiz de Clavijo Vázquez, Paulino | es |
dc.creator | Ostúa Arangüena, Enrique | es |
dc.date.accessioned | 2024-01-08T10:36:36Z | |
dc.date.available | 2024-01-08T10:36:36Z | |
dc.date.issued | 2020 | |
dc.identifier.citation | Guerrero Martos, D., Cano Quiveu, G., Juan Chico, J., Millán Calderón, A., Bellido Díaz, M.J., Viejo Cortés, J.,...,Ostúa Arangüena, E. (2020). Address encoded byte order. Microprocessors and Microsystems, 78 (103268) https://doi.org/10.1016/j.micpro.2020.103268. | |
dc.identifier.issn | 0141-9331 | es |
dc.identifier.uri | https://hdl.handle.net/11441/153011 | |
dc.description.abstract | Unaligned accesses are forbidden in many high-performance architectures. In most of these architectures, the
least significant address bits of a multibyte memory access must be zero. Otherwise, the program generating
the access is considered erroneous and an exception is flagged. The objective of this paper is to propose an
alternative behaviour using the least significant address bits to encode the byte order of the accessed data.
Modifying a traditional architecture to support the proposed behaviour presents several advantages, including
backward compatibility at binary-code level, and the possibility of carrying out an endianness conversion
during multibyte memory accesses without increasing the execution time nor using additional opcodes. The
technique is demonstrated by modifying an OpenRISC 1000 implementation without introducing any penalty
in hardware resources or performance. Subroutines written and compiled for the traditional architecture and
originally designed for only the native byte order can, in the modified architecture, read and write data in
a non-native byte order without any need to recompile. The execution of a sample algorithm operating on
non-native byte order shows a reduction of 60% in the user execution time in the modified implementation
when compared to the original implementation. | es |
dc.description.sponsorship | Ministerio de Economía, Industria y Competitividad (España) TIN2017-89951-P | es |
dc.format | application/pdf | es |
dc.format.extent | 9 p. | es |
dc.language.iso | eng | es |
dc.publisher | Elsevier B.V. | es |
dc.relation.ispartof | Microprocessors and Microsystems, 78 (103268) | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | ISA | es |
dc.subject | Data alignment | es |
dc.subject | Byte order | es |
dc.subject | Endianness | es |
dc.subject | Shared memory | es |
dc.subject | MPSoC | es |
dc.title | Address encoded byte order | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/publishedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.projectID | TIN2017-89951-P | es |
dc.relation.publisherversion | https://www.sciencedirect.com/science/article/pii/S0141933120304270 | es |
dc.identifier.doi | 10.1016/j.micpro.2020.103268 | es |
dc.journaltitle | Microprocessors and Microsystems | es |
dc.publication.volumen | 78 | es |
dc.publication.issue | 103268 | es |
dc.publication.initialPage | 103268 | es |
dc.contributor.funder | European Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER) | es |
dc.contributor.funder | Ministerio de
Economía, Industria y Competitividad (España) | |