Static Linearity BIST for Vcm-based Switching SAR ADCs Using a Reduced-code Measurement Technique

Abstract

This work presents a reduced-code strategy for the static linearity self-testing of Vcm -based successive-approximation analog to digital converters (SAR ADCs). These techniques take advantage of the repetitive operation of SAR ADCs for reducing the number of necessary measurements for static linearity testing. In this paper we discuss the application of these techniques for the Vcm-based SAR ADC topology and present a practical BIST implementation based on an embedded incremental ADC. Electrical simulation results at transistor level are presented to validate the feasibility of the proposed on-chip reduced-code static linearity test.