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dc.creatorPaul, Aninditaes
dc.creatorRamírez Angulo, Jaimees
dc.creatorLópez Martín, Antonio J.es
dc.creatorGonzález Carvajal, Ramónes
dc.date.accessioned2023-01-20T09:24:17Z
dc.date.available2023-01-20T09:24:17Z
dc.date.issued2018
dc.identifier.citationPaul, A., Ramírez Angulo, J., López Martín, A.J. y González Carvajal, R. (2018). CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27 (2), 294-303. https://doi.org/10.1109/TVLSI.2018.2878017.
dc.identifier.issn1063-8210es
dc.identifier.urihttps://hdl.handle.net/11441/141624
dc.description.abstractA CMOS fully integrated all-pass filter with an extremely low pole frequency of 2 Hz is introduced in this paper. It has 0.08-dB passband ripple and 0.029-mm 2 Si area. It has 0.38-mW power consumption in strong inversion with ±0.6-V power supplies. In subthreshold, it has 0.64-μW quiescent power and operates with ±200-mV dc supplies. Miller multiplication is used to obtain a large equivalent capacitor without excessive Si area. By varying the gain of the Miller amplifier, the pole frequency can be varied from 2 to 48 Hz. Experimental and simulation results of a test chip prototype in 130-nm CMOS technology validate the proposed circuit.es
dc.formatapplication/pdfes
dc.format.extent10 p.es
dc.language.isoenges
dc.publisherIEEE (Institute of Electrical and Electronics Engineers)es
dc.relation.ispartofIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27 (2), 294-303.
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectAll-pass filter (APF)es
dc.subjectAmplifieres
dc.subjectMiller multiplieres
dc.subjectOperational transconductance amplifier (OTA)es
dc.subjectVoltage followeres
dc.titleCMOS First-Order All-Pass Filter With 2-Hz Pole Frequencyes
dc.typeinfo:eu-repo/semantics/articlees
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Ingeniería Electrónicaes
dc.relation.publisherversionhttps://ieeexplore.ieee.org/abstract/document/8528883es
dc.identifier.doi10.1109/TVLSI.2018.2878017es
dc.journaltitleIEEE Transactions on Very Large Scale Integration (VLSI) Systemses
dc.publication.volumen27es
dc.publication.issue2es
dc.publication.initialPage294es
dc.publication.endPage303es

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Except where otherwise noted, this item's license is described as: Attribution-NonCommercial-NoDerivatives 4.0 Internacional