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dc.creatorPourashraf, Shirines
dc.creatorRamírez Angulo, Jaimees
dc.creatorHinojo Montero, José Maríaes
dc.creatorGonzález Carvajal, Ramónes
dc.creatorLópez Martín, Antonio J.es
dc.date.accessioned2023-01-20T09:02:11Z
dc.date.available2023-01-20T09:02:11Z
dc.date.issued2019
dc.identifier.citationPourashraf, S., Ramírez Angulo, J., Hinojo Montero, J.M., González Carvajal, R. y López Martín, A.J. (2019). ±0.25-V Class-AB CMOS Capacitance Multiplier and Precision Rectifiers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27 (4), 830-842. https://doi.org/10.1109/TVLSI.2018.2881249.
dc.identifier.issn1063-8210es
dc.identifier.urihttps://hdl.handle.net/11441/141623
dc.description.abstractReduction of minimum supply requirements is a crucial aspect to decrease the power consumption in VLSI systems. A high-performance capacitance multiplier able to operate with supplies as low as ±0.25 V is presented. It is based on adaptively biased class-AB current mirrors which provide high current efficiency. Measurement results of a factor 11 capacitance multiplier fabricated in 180-nm CMOS technology verify theoretical claims. Moreover, low-voltage precision rectifiers based on the same class-AB current mirrors are designed and fabricated in the same CMOS process. They generate output currents over 100 times larger than the quiescent current. Both proposed circuits have 300-nW static power dissipation when operating with ±0.25-V supplies.es
dc.formatapplication/pdfes
dc.format.extent13 p.es
dc.language.isoenges
dc.publisherIEEE (Institute of Electrical and Electronics Engineers)es
dc.relation.ispartofIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27 (4), 830-842.
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectCapacitance multiplieres
dc.subjectClass-AB current mirrores
dc.subjectLow supply voltagees
dc.subjectPrecision rectifierses
dc.title±0.25-V Class-AB CMOS Capacitance Multiplier and Precision Rectifierses
dc.typeinfo:eu-repo/semantics/articlees
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Ingeniería Electrónicaes
dc.relation.publisherversionhttps://ieeexplore.ieee.org/abstract/document/8573900es
dc.identifier.doi10.1109/TVLSI.2018.2881249es
dc.journaltitleIEEE Transactions on Very Large Scale Integration (VLSI) Systemses
dc.publication.volumen27es
dc.publication.issue4es
dc.publication.initialPage830es
dc.publication.endPage842es

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