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dc.creatorNúñez Martínez, Juanes
dc.creatorAvedillo de Juan, María Josées
dc.creatorQuintana Toledo, José Maríaes
dc.date.accessioned2022-07-13T11:24:55Z
dc.date.available2022-07-13T11:24:55Z
dc.date.issued2013
dc.identifier.citationNúñez Martínez, J., Avedillo de Juan, M.J. y Quintana Toledo, J.M. (2013). Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications. En PATMOS 2012 International Workshop on Power and Timing Modeling, Optimization and Simulation (166-174), Newcastle, UK: Springer.
dc.identifier.isbn978-3-642-36156-2es
dc.identifier.urihttps://hdl.handle.net/11441/135309
dc.description.abstractMonostable to Bistable (MOBILE) gates are very suitable for the implementation of gate-level pipelines which can be achieved without resorting to memory elements. MOBILE operating principle is implemented using two series connected Negative Differential Resistance (NDR) devices with a clocked bias. This paper describes and experimentally validates a two-phase clock scheme for such MOBILE based ultra-grain pipelines. Up to our knowledge it is the first MOBILE working circuit reported with this interconnection architecture. The proposed interconnection architecture is applied to the design of a 4-bit Carry Look-ahead Adder.es
dc.description.sponsorshipMinisterio de Economía y Competitividad del Gobierno de España with support from ERDF under Project TEC2010-18937es
dc.format.extent9 p.es
dc.language.isoenges
dc.publisherSpringeres
dc.relation.ispartofPATMOS 2012 International Workshop on Power and Timing Modeling, Optimization and Simulation (2013), pp. 166-174.
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectNegative Differential Resistance (NDR)es
dc.subjectNanopipelinees
dc.subjectMonostable to Bistable Logic Elements (MOBILE)es
dc.titleTwo-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applicationses
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.projectIDTEC2010-18937es
dc.relation.publisherversionhttps://dx.doi.org/10.1007/978-3-642-36157-9_17es
dc.identifier.doi10.1007/978-3-642-36157-9_17es
dc.publication.initialPage166es
dc.publication.endPage174es
dc.eventtitlePATMOS 2012 International Workshop on Power and Timing Modeling, Optimization and Simulationes
dc.eventinstitutionNewcastle, UKes
dc.contributor.funderMinisterio de Economía y Competitividad (MINECO). Españaes
dc.contributor.funderEuropean Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER)es

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