dc.creator | Rico-Aniles, Héctor Daniel | es |
dc.creator | Ramírez Angulo, Jaime | es |
dc.creator | López-Martín, Antonio J. | es |
dc.creator | González Carvajal, Ramón | es |
dc.creator | Rocha-Pérez, José Miguel | es |
dc.creator | Garde, M. Pilar | es |
dc.date.accessioned | 2021-07-29T11:18:14Z | |
dc.date.available | 2021-07-29T11:18:14Z | |
dc.date.issued | 2020 | |
dc.identifier.citation | Rico-Aniles, H.D., Ramírez Angulo, J., López-Martín, A.J., González Carvajal, R., Rocha-Pérez, J.M. y Garde, M.P. (2020). Power Efficient Simple Technique to Convert a Reset-and-Hold Into a True-Sample-and-Hold Using an Auxiliary Output Stage. IEEE Access, 8, 66508-66516. | |
dc.identifier.issn | 2169-3536 | es |
dc.identifier.uri | https://hdl.handle.net/11441/116545 | |
dc.description.abstract | A technique to implement true-sample-and-hold circuits that hold the output for almost the
entire clock cycle without resetting to zero is introduced, alleviating the slew rate requirement on the op-amp.
It is based on a Miller op-amp with an auxiliary output stage that increases power dissipation by only 1.3%.
The circuit is offset-compensated and has close to rail-to-rail swing. Experimental results of a test chip
prototype in 130nm CMOS technology with 0.3mW power dissipation are provided, which validate the
proposed technique. | es |
dc.description.sponsorship | Consejo Nacional de Ciencia y Tecnologia (CONACYT) (México) 408946 | es |
dc.description.sponsorship | Unión Europea TEC2016-80396-C2 (AEI/FEDER) | es |
dc.format | application/pdf | es |
dc.format.extent | 9 p. | es |
dc.language.iso | eng | es |
dc.publisher | IEEE | es |
dc.relation.ispartof | IEEE Access, 8, 66508-66516. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Ampli ers | es |
dc.subject | mixed-signal circuits | es |
dc.subject | offset compensation | es |
dc.subject | track-and-hold | es |
dc.subject | sample-andhold (S/H) | es |
dc.subject | switched capacitor | es |
dc.title | Power Efficient Simple Technique to Convert a Reset-and-Hold Into a True-Sample-and-Hold Using an Auxiliary Output Stage | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/publishedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Ingeniería Electrónica | es |
dc.relation.projectID | TEC2016-80396-C2 (AEI/FEDER) | es |
dc.relation.projectID | 408946 | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/9055423 | es |
dc.identifier.doi | 10.1109/ACCESS.2020.2985256 | es |
dc.journaltitle | IEEE Access | es |
dc.publication.volumen | 8 | es |
dc.publication.initialPage | 66508 | es |
dc.publication.endPage | 66516 | es |