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Ponencia
Learning VHDL through teamwork FPGA game design
(IEEE Computer Society, 2020)
The learning of digital design at the RT level by the students improves with practical work, which can be developed in teams, allow both the gradual advance of complexity as the learning progresses, and the proposal to ...
Ponencia
Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher
(IEEE Computer Society, 2018)
The fault injection in ciphers operation is a very successful mechanism to attack them. The inclusion of elements of protection against this kind of attacks is more and more necessary. These mechanisms are usually based ...