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Artículo
Signal Sampling Based Transition Modeling for Digital Gates Characterization
(Springer, 2004)
Current characterization methods introduce an important error in the measurement process. In this paper, we present a novel method to drive the timing characterization of logic gates under variable input transition times. ...
Artículo
Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)
(Springer, 2002-08-27)
In previous papers we have presented a very accurate model that handles the generation and propagation of glitches, which makes an important headway in logic timing simulation. This model is called Delay Degradation Model ...
Artículo
Automated performance evaluation of skew-tolerant clocking schemes
(Taylor and Francis Online, 2006)
In this paper the authors evaluate the timing and power performance of three skew-tolerant clocking schemes. These schemes are the well known master–slave clocking scheme (MS) and two schemes developed by the authors: ...