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Mostrando ítems 61-70 de 85
Artículo
An Instant-Startup Jitter-Tolerant Manchester- Encoding Serializer/Deserializer Scheme for Event-Driven Bit-Serial LVDS Interchip AER Links
(IEEE Computer Society, 2011)
This paper presents a serializer/deserializer scheme for asynchronous address event representation (AER) bit-serial interchip communications. Each serial AER (sAER) link uses four wires: a micro strip pair for low voltage ...
Ponencia
Hardware Implementation of Convolutional STDP for On-line Visual Feature Learning
(IEEE. Institute of Electrical and Electronics Engineers, 2017)
We present a highly hardware friendly STDP (Spike Timing Dependent Plasticity) learning rule for training Spiking Convolutional Cores in Unsupervised mode and training Fully Connected Classifiers in Supervised ...
Ponencia
Synthetic Generation of Events for Address-Event-Representation Communications
(Springer, 2002)
Address-Event-Representation (AER) is a communications protocol for transferring images between chips, originally developed for bio-inspired image processing systems. Such systems may consist of a complicated hierarchical ...
Artículo
A Low-Power Current Mode Fuzzy-ART Cell
(IEEE Computer Society, 2006)
This paper presents a very large scale integration (VLSI) implementation of a low-power current-mode fuzzy-adaptive resonance theory (ART) cell. The cell is based on a compact new current source multibit memory cell ...
Ponencia
Spike-Based Convolutional Network for real-time processing
(IEEE Computer Society, 2010)
In this paper we propose the first bio-inspired sixlayer convolutional network (ConvNet) non-frame based that can be implemented with already physically available spikebased electronic devices. The system was designed ...
Artículo
STDP and STDP Variations with Memristors for Spiking Neuromorphic Learning Systems
(2013)
In this paper we review several ways of realizing asynchronous Spike-Timing-DependentPlasticity (STDP) using memristors as synapses. Our focus is on how to use individual memristors to implement synaptic weight ...
Artículo
Neuromorphic Spiking Neural Networks and Their Memristor-CMOS Hardware Implementations
(MDPI, 2019)
Inspired by biology, neuromorphic systems have been trying to emulate the human brain for decades, taking advantage of its massive parallelism and sparse information coding. Recently, several large-scale hardware projects ...
Ponencia
Multiplexing AER Asynchronous Channels over LVDS Links with Flow-Control and Clock-Correction for Scalable Neuromorphic Systems
(IEEE Computer Society, 2017)
Address-Event-Representation (AER) is a widely extended asynchronous technique for interchanging “neural spikes” among different hardware elements in Neuromorphic Systems. Conventional AER links use parallel physical ...
Ponencia
High-Speed Serial Interfaces for Event-Driven Neuromorphic Systems
(IEEE Computer Society, 2015)
Neuromorphic Engineering is the discipline of building sensory processing artificial systems inspired in the neural processing found in living beings. Biological neural brains show massive connectivity among neurons, ...
Artículo
Inter-spike-intervals analysis of AER Poisson-like generator hardware
(Elsevier, 2007)
Address–Event–Representation (AER) is a communication protocol for transferring images between chips, originally developed for bio-inspired image-processing systems. Such systems may consist of a complicated hierarchical ...