dc.creator | Parsakordasiabi, Mojtaba | es |
dc.creator | Vornicu, Ion | es |
dc.creator | Rodríguez Vázquez, Ángel Benito | es |
dc.creator | Carmona Galán, Ricardo | es |
dc.date.accessioned | 2021-06-15T13:40:46Z | |
dc.date.available | 2021-06-15T13:40:46Z | |
dc.date.issued | 2021 | |
dc.identifier.citation | Parsakordasiabi, M., Vornicu, I., Rodríguez Vázquez, Á.B. y Carmona Galán, R. (2021). A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA. Sensors, 21 (1), 308. | |
dc.identifier.issn | 1424-8220 | es |
dc.identifier.uri | https://hdl.handle.net/11441/111813 | |
dc.description.abstract | In this paper, we present a proposed field programmable gate array (FPGA)-based time-to-digital converter (TDC) architecture to achieve high performance with low usage of resources. This TDC can be employed for multi-channel direct Time-of-Flight (ToF) applications. The proposed architecture consists of a synchronizing input stage, a tuned tapped delay line (TDL), a combinatory encoder of ones and zeros counters, and an online calibration stage. The experimental results of the TDC in an Artix-7 FPGA show a differential non-linearity (DNL) in the range of [−0.953, 1.185] LSB, and an integral non-linearity (INL) within [−2.750, 1.238] LSB. The measured LSB size and precision are 22.2 ps and 26.04 ps, respectively. Moreover, the proposed architecture requires low FPGA resources. | es |
dc.description.sponsorship | European Union 765866 | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad RTI2018-097088-B-C31 | es |
dc.description.sponsorship | US Office of Naval Research N00014-19-1-2156 | es |
dc.format | application/pdf | es |
dc.format.extent | 15 p. | es |
dc.language.iso | eng | es |
dc.publisher | Multidisciplinary Digital Publishing Institute (MDPI) | es |
dc.relation.ispartof | Sensors, 21 (1), 308. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Field programmable gate array (FPGA) | es |
dc.subject | Tapped-delay-line (TDL) | es |
dc.subject | Thermometer-to-binary (T2B) encoder | es |
dc.subject | Multichannel TDCs | es |
dc.subject | Time-to-digital converter (TDC) | es |
dc.subject | Time-of-flight (ToF) | es |
dc.subject | Singlephoton avalanche diode (SPAD) | es |
dc.title | A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/publishedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | 765866 | es |
dc.relation.projectID | RTI2018-097088-B-C31 | es |
dc.relation.projectID | N00014-19-1-2156 | es |
dc.relation.publisherversion | https://doi.org/10.3390/s21010308 | es |
dc.identifier.doi | 10.3390/s21010308 | es |
dc.journaltitle | Sensors | es |
dc.publication.volumen | 21 | es |
dc.publication.issue | 1 | es |
dc.publication.initialPage | 308 | es |