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Ponencia
Convergence and stability of the FSR CNN model
(Institute of Electrical and Electronics Engineers, 1994)
Stability and convergency results are reported for a modified continuous-time CNN model. The signal range of the state variables is equal to the unitary interval, independently of the application. Stability and convergency ...
Ponencia
A mixed-signal early vision chip with embedded image and programming memories and digital I/O
(The International Society for Optical Engineering - SPIE, 2003)
From a system level perspective, this paper presents a 128 × 128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35μm standard digital 1P-5M CMOS ...
Ponencia
Hybrid-control of synapse circuits for programmable cellular neural networks
(Institute of Electrical and Electronics Engineers, 1996)
This paper describes a hybrid weight-control strategy for VLSI realizations of programmable Cellular Neural Networks (CNNs), based on auto-tuning of analog control signals to digitally specified values. The approach merges ...
Ponencia
Structure reconfigurability of the CNNUC3 for robust template operation
(Institute of Electrical and Electronics Engineers, 2000)
We demonstrate the importance of the reconfigurability of a 64/spl times/64 cells size CNN-UM chip. As we show, in such a high complexity mixed-signal VLSI circuit the switch and internal reference level reconfigurability ...
Ponencia
A countinuous-time cellular neural network chip for direction-selectable connected component detection with optical image acquisition
(Institute of Electrical and Electronics Engineers, 1994)
This paper presents a continuous-time Cellular Neural Network (CNN) chip [1] for the application of Connected Component Detection (CCDet) [2]. Projection direction can be selected among four different possibilities. Every ...
Ponencia
Mixed-signal CNN array chips for image processing
(The International Society for Optical Engineering, 1996)
Due to their local connectivity and wide functional capabilities, cellular nonlinear networks (CNN) are excellent candidates for the implementation of image processing algorithms using VLSI analog parallel arrays. However, ...
Ponencia
Analog weight buffering strategy for CNN chips
(Institute of Electrical and Electronics Engineers, 2003)
Large, gray-scale CNN chips employ analog signals to achieve high-density in the internal distribution of the template parameters. Despite the design strategies adopted at the circuitry employed to implement the weights, ...
Ponencia
Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics
(Institute of Electrical and Electronics Engineers, 2002)
A bio-inspired model for an analog parallel array processor (APAP), based on studies on the vertebrate retina, permits the realization of complex spatio-temporal dynamics in VLSI. This model mimics the way in which images ...
Ponencia
Design of a programmable mixed-signal CMOS image-processing chip in 0.8 /spl mu/m CMOS
(Institute of Electrical and Electronics Engineers, 1997)
An operational vision-chip prototype with a wide-range of potential applications in artificial-vision systems is presented. Its functionality includes concurrent image-transduction, programmable image-processing, image-storage, ...
Ponencia
Object oriented image segmentation on the CNNUC3 chip
(Institute of Electrical and Electronics Engineers, 2000)
We show how a complex object oriented image analysis algorithm can be implemented on a CNNUM chip for video-coding. Besides the applied linear operations, several gray-scale nonlinear template operations are also emulated ...