Browsing Artículos (Instituto de Microelectrónica de Sevilla (IMSE-CNM)) by Subject "Design methodology"
Now showing items 1-5 of 5
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Article
Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits
(Institute of Electrical and Electronics Engineers, 2009)We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with ...
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Article
Design methodology for low-jitter differential clock recovery circuits in high performance ADCs
(Springer, 2016)This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low ...
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Article
Integrated chaos generators
(Institute of Electrical and Electronics Engineers, 2002)This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.
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Article
MOST moderate-weak-inversion region as the optimum design zone for CMOS 2.4-GHz CS-LNAs
(Institute of Electrical and Electronics Engineers, 2014)In this paper, the MOS transistor (MOST) moderate-inversion (MI)-weak-inversion (WI) region is shown to be the optimum ...
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Article
Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm
(Institute of Electrical and Electronics Engineers, 2011)A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map ...