Now showing items 1-17 of 17

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      A 515 nW, 0-18 dB programmable gain analog-to-digital converter for in-channel neural recording interfaces  [Article]

      Rodríguez Pérez, Alberto; Delgado Restituto, Manuel ; Medeiro Hidalgo, Fernando (Institute of Electrical and Electronics Engineers, 2014)
      This paper presents a low-area low-power Switched-Capacitor (SC)-based Programmable-Gain Analog-to-Digital Converter (PG-ADC) suitable for in-channel neural recording applications. The PG-ADC uses a novel implementation ...
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      A Low Noise Amplifier for Neural Spike Recording Interfaces  [Article]

      Ruiz Amaya, Jesús; Rodríguez Pérez, Alberto; Delgado Restituto, Manuel  (Multidisciplinary Digital Publishing Institute, 2015)
      This paper presents a Low Noise Amplifier (LNA) for neural spike recording applications. The proposed topology, based on a capacitive feedback network using a two-stage OTA, efficiently solves the triple trade-off between ...
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      An Event-Driven Classifier for Spiking Neural Networks Fed with Synthetic or Dynamic Vision Sensor Data  [Article]

      Stromatias, Evangelos; Soto, Miguel; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (Frontiers Media, 2017)
      This paper introduces a novel methodology for training an event-driven classifier within a Spiking Neural Network (SNN) System capable of yielding good classification results when using both synthetic input data and real ...
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      Closed-loop Simulation Method for Evaluation of Static Offset in Discrete-Time Comparators  [Article]

      Ginés Arteaga, Antonio José; Peralías Macías, Eduardo; Léger, Gildas; Rueda Rueda, Adoración (Institute of Electrical and Electronics Engineers, 2014)
      This paper presents a simulation-based method for evaluating the static offset in discrete-time comparators. The proposed procedure is based on a closed-loop algorithm which forces the input signal of the comparator to ...
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      Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas  [Article]

      Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2016)
      In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than ...
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      Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs  [Article]

      Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2017)
      Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this ...
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      Compensation of PVT Variations in ToF Imagers with In-Pixel TDC  [Article]

      Rodríguez Vázquez, Ángel Benito; Vornicu, Ion; Carmona Galán, Ricardo (MDPI, 2017)
      The design of a direct time-of-flight complementary metal-oxide-semiconductor (CMOS) image sensor (dToF-CIS) based on a single-photon avalanche-diode (SPAD) array with an in-pixel time-to-digital converter (TDC) must ...
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      Efficient Hybrid Continuous-Time/Discrete-Time Cascade Modulators for Wideband Applications  [Article]

      García Sánchez, Gerardo; Rosa Utrera, José Manuel de la (Elsevier, 2014)
      This paper analyses the use of hybrid continuous-time/discrete-time cascade ΣΔ modulators for the implementation of power-efficient analog-to-digital converters in broadband wireless communication systems. Two alternative ...
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      Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements  [Article]

      Nuñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2014)
      Abstract: Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable (MOBILE) gates are very suitable for implementing gate-level pipelines, which can be achieved without ...
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      FLIP-Q: A QCIF resolution focal-plane array for low-power image processing  [Article]

      Fernández Berni, Jorge; Carmona Galán, Ricardo; Carranza González, Luis (Institute of Electrical and Electronics Engineers, 2011)
      This paper reports a 176×144-pixel smart image sensor designed and fabricated in a 0.35 CMOS-OPTO process. The chip implements a massively parallel focal-plane processing array which can output different simplified ...
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      Insights Into the Operation of Hyper-FET-Based Circuits  [Article]

      Avedillo de Juan, María José; Nuñez Martínez, Juan (Institute of Electrical and Electronics Engineers, 2017)
      Devices combining transistors and phase transition materials are being investigated to obtain steep switching and a boost in the ION/IOFF ratio and, thus, to solve power and energy limitations of CMOS technologies. This ...
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      Parametric macromodeling of integrated inductors for RF circuit design  [Article]

      Passos, Fabio; Ye, Y.; Spina, D.; Roca Moreno, Elisenda; Castro López, Rafael; Dhaene, T.; Fernández Fernández, Francisco Vidal (Wiley-Blackwell, 2017)
      Nowadays, parametric macromodeling techniques are widely used to describe electromagnetic structures. In this contribution, the application of such parametric macromodeling techniques to the design of integrated inductors ...
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      Reducing the Impact of Reverse Currents in Tunnel FET Rectifiers for Energy Harvesting Applications  [Article]

      Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2017)
      RF to DC passive rectifiers can benefit from the superior performance at low voltage of tunnel transistors. They have shown higher power conversion efficiency (PCE) at low input power than Si FinFETs counterparts. In this ...
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      Semi-empirical RF MOST model for CMOS 65 nm technologies: theory, extraction method and validation  [Article]

      Fiorelli, Rafaella; Peralías Macías, Eduardo (Elsevier, 2016)
      This paper presents a simple but accurate semi-empirical model especially focused on 65 nm MOST (MOS transistor) technologies and radio-frequency (RF) applications. It is obtained by means of simple dc and noise simulations ...
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      Smart imaging for power-efficient extraction of Viola-Jones local descriptors  [Article]

      Fernández Berni, Jorge; Carmona Galán, Ricardo; Río Fernández, Rocío del; Leñero Bardallo, Juan Antonio; Suárez Cambre, Manuel; Rodríguez Vázquez, Ángel Benito (Society of Photo-Optical Instrumentation Engineers, 2014)
      In computer vision, local descriptors permit to summarize relevant visual cues through feature vectors. These vectors constitute inputs for trained classifiers which in turn enable different high-level vision tasks. While ...
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      System-Level Design of a 64-Channel Low Power Neural Spike Recording Sensor  [Article]

      Delgado Restituto, Manuel; Rodríguez Pérez, Alberto; Darie, Ángela; Soto Sánchez, Cristina; Fernández Jover, Eduardo; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2017)
      This paper reports an integrated 64-channel neural spike recording sensor, together with all the circuitry to process and configure the channels, process the neural data, transmit via a wireless link the information and ...
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      The bio-oscillator: A circuit for cell-culture assays  [Article]

      Huertas Sánchez, Gloria; Maldonado-Jacobi, Andrés; Yúfera García, Alberto; Rueda Rueda, Adoración; Huertas Díaz, José Luis (Institute of Electrical and Electronics Engineers, 2015)
      A system for cell-culture real-time monitoring using an oscillation-based approach is proposed. The system transforms a cell culture under test into a suitable “biological” oscillator, without needing complex circuitry for ...