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Mostrando ítems 1-10 de 25
Ponencia
A mixed-signal early vision chip with embedded image and programming memories and digital I/O
(The International Society for Optical Engineering - SPIE, 2003)
From a system level perspective, this paper presents a 128 × 128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35μm standard digital 1P-5M CMOS ...
Artículo
Compact low-power calibration mini-DACs for neural arrays with programmable weights
(Institute of Electrical and Electronics Engineers, 2003)
This paper considers the viability of compact low-resolution low-power mini digital-to-analog converters (mini-DACs) for use in large arrays of neural type cells, where programmable weights are required. Transistors are ...
Ponencia
Design Considerations for an Automotive Sensor Interface Sigma-Delta Modulator
(Institute of Electrical and Electronics Engineers, 2003)
The Sigma-Delta Modulator presented in this paper contains a programmable-gain input inferface to accommodate the output signal level of a variety of automotive sensors. We show that this characteristic can be efficiently ...
Ponencia
Analog weight buffering strategy for CNN chips
(Institute of Electrical and Electronics Engineers, 2003)
Large, gray-scale CNN chips employ analog signals to achieve high-density in the internal distribution of the template parameters. Despite the design strategies adopted at the circuitry employed to implement the weights, ...
Artículo
A Bio-Inspired Two-Layer Mixed-Signal Flexible Programmable Chip for Early Vision
(Institute of Electrical and Electronics Engineers, 2003)
A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynamics in VLSI. This model mimics ...
Ponencia
On the development of a MODEM for data transmission and control of electrical household appliances using the low-voltage power-line
(Institute of Electrical and Electronics Engineers, 2003)
This paper presents a CMOS 0,6μm mixed-signal MODEM ASIC for data transmission on the low-voltage power line. The circuit includes all the analog circuitry needed for input interfacing and modulation/demodulation (PLL-based ...
Artículo
Log-domain implementation of complex dynamics reaction-diffusion neural networks
(Institute of Electrical and Electronics Engineers, 2003)
In this paper, we have identified a second-order reaction-diffusion differential equation able to reproduce through parameter setting different complex spatio-temporal behaviors. We have designed a log-domain hardware that ...
Ponencia
Expandible high-order cascade ya modulator with constant, reduced systematic loss of resolution
(Institute of Electrical and Electronics Engineers, 2003)
An arbitrary order sigma-delta modulator cascude architecture is presented with only I-bit loss of resolution due to scaling issues, even with single-bit quantizulion. This loss is kept with a high overloading point, ...
Ponencia
Accurate VHDL-based simulation of Sigma Delta modulators
(Institute of Electrical and Electronics Engineers, 2003)
The computational cost of transient simulation of /spl Sigma//spl Delta/ modulators (/spl Sigma//spl Delta/Ms) at the electrical level is prohibitively high. Behavioral simulation techniques offer a promising solution to ...
Artículo
1 V CMOS subthreshold log domain PDM
(Springer, 2003)
A new CMOS circuit strategy for very low-voltage Pulse-Duration Modulators (PDM) is proposed. Optimization of voltage supply scaling below the sum of threshold voltages is based on Instantaneous Log Companding processing ...